Synopsys Interview Questions, Process, and Tips

Q1. FPGA architecture
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Q2. Static Timing Analysis
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Resume based questions

Q1. Questions based on SERDES
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Q1. I am from a software background. My work is Automation in ASIC IP flow. They focused on the software life cycle questions, oops conceps, basic programming
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Q1. Its focused on problem solving abilities. They put a problem and asked to write code. They check for the approach.
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Q1. Its in general for me. Not difficult at all
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Question on SDLC and challenges in Documentation process.
Writing test to check DITA proficiency on Framemaker/Oxygen
Write an email to inform release manager why you skipped a mapper release update in documentation
Basic grammar test

Interview with team members and Manger about writing style and documentation

Q1. DESIGN A MOD COUNTER
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A mod counter is a counter that counts from 0 to a specified modulus value before resetting to 0.
• Design a counter with a specified number of bits to represent the count value

• Implement logic to increment the count value by 1

• Add logic to reset the count value to 0 when it reaches the modulus value
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Q2. DIFFERENCE BTW LATCH AND FLIPFLOP
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A latch is level sensitive and a flip-flop is edge sensitive. Latch changes output as soon as input changes, while flip-flop changes output only on clock edge.
• Latch is level triggered, while flip-flop is edge triggered

• Latch changes output as soon as input changes, while flip-flop changes output only on clock edge

• Latch is asynchronous, while flip-flop is synchronous

• Examples: SR latch, D latch for latch; D flip-flop, JK
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Questions regarding ArrayList, String, and Set.

Questions on programming logics, solving puzzles

Q1. Techno managerial round focusing on automation framework and qa practices
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Q1. HR discussion, salary negotiation
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