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Synopsys Asic Design Verification Engineer Interview Questions and Answers

Updated 10 Jan 2025

Synopsys Asic Design Verification Engineer Interview Experiences

2 interviews found

Interview experience
5
Excellent
Difficulty level
-
Process Duration
-
Result
-
Round 1 - HR 

(2 Questions)

  • Q1. Why do you want to work at Synopsys?
  • Ans. 

    I want to work at Synopsys because of their reputation for innovation and cutting-edge technology in the field of ASIC design verification.

    • Synopsys is a leader in the EDA industry, known for their advanced tools and solutions for semiconductor design.

    • I am impressed by Synopsys' commitment to research and development, which aligns with my passion for pushing the boundaries of technology.

    • I believe working at Synopsys wil...

  • Answered by AI
  • Q2. Talk us a little bit about yourself

Interview Preparation Tips

Interview preparation tips for other job seekers - It's easy, just study basic electronics like flip flops and minor circuits.

I applied via Campus Placement and was interviewed in Oct 2021. There were 3 interview rounds.

Round 1 - Aptitude Test 

3 sections in exam
Aptitude,digital and verilog
Gate previous year will do for digital

Round 2 - Technical 

(1 Question)

  • Q1. Basic digital like difference between latch and flipflop,Moore vs mealey which one is better
Round 3 - Technical 

(1 Question)

  • Q1. Verilog coding A 100hz square wave signal 50 percent duty cycle is given Write verilog code for dividing frequency of signal by 3.
  • Ans. 

    Verilog code to divide frequency of a 100hz square wave signal with 50% duty cycle by 3.

    • Create a counter that counts up to 3 and resets back to 0

    • Use the counter to toggle an output signal every 3 cycles of the input signal

    • The output signal will have a frequency of 100/3 = 33.33hz with 50% duty cycle

  • Answered by AI

Interview Preparation Tips

Interview preparation tips for other job seekers - Be strong in verilog and be little thorough with what you did in internship

Skills evaluated in this interview

Asic Design Verification Engineer Interview Questions Asked at Other Companies

asked in Synopsys
Q1. Verilog coding A 100hz square wave signal 50 percent duty cycle i ... read more
Q2. how to predict if a 32 bit number is divisible by 8, draw a circu ... read more
Q3. Conversation one number system to other. Make nand gate using Mux ... read more
Q4. Whats a bus functional model and how it's written
asked in Synopsys
Q5. Why do you want to work at Synopsys?

Interview questions from similar companies

Interview experience
4
Good
Difficulty level
Hard
Process Duration
Less than 2 weeks
Result
Selected Selected

I applied via campus placement at Indian Institute of Technology (IIT), Kanpur and was interviewed before Mar 2023. There was 1 interview round.

Round 1 - Technical 

(5 Questions)

  • Q1. Design of mux and ff
  • Ans. 

    A multiplexer (mux) is a digital circuit that selects one of several input signals and forwards it to a single output. A flip-flop (ff) is a type of latch circuit that stores a single bit of data.

    • Mux design involves selecting one of multiple input signals based on a control signal

    • FF design involves storing a single bit of data using a clock signal

    • Mux can be implemented using logic gates like AND, OR, and NOT gates

    • FF ca...

  • Answered by AI
  • Q2. Basics of sv n verilog
  • Q3. Sta question about timing violation
  • Q4. Thesis related question
  • Q5. Some basic design question

Interview Preparation Tips

Interview preparation tips for other job seekers - good at basics of sta, sv and uvm
Interview experience
3
Average
Difficulty level
-
Process Duration
-
Result
-
Round 1 - Technical 

(2 Questions)

  • Q1. Toggle the bits of given input
  • Ans. 

    Toggle the bits of given input

    • Create a mask with all bits set to 1

    • XOR the input with the mask to toggle the bits

    • Repeat the process for each bit position

  • Answered by AI
  • Q2. Clear the set bit
Round 2 - Technical 

(2 Questions)

  • Q1. Print the star pattern
  • Ans. 

    Print a star pattern using loops

    • Use nested loops to print the desired pattern

    • Increment the number of stars in each row to create the pattern

    • Example: for a pattern with 5 rows - * , ** , *** , **** , *****

  • Answered by AI
  • Q2. Microprocessor microcontroller topics are asked

Skills evaluated in this interview

Interview experience
4
Good
Difficulty level
-
Process Duration
-
Result
-
Round 1 - Technical 

(1 Question)

  • Q1. Write a FIFO checker
  • Ans. 

    A FIFO checker is a verification component used to monitor and validate the behavior of a First-In-First-Out buffer in a design.

    • Implement a monitor that tracks the input and output operations of the FIFO buffer

    • Check that the data is read out in the same order it was written in

    • Verify that the FIFO buffer does not overflow or underflow

    • Use assertions to flag any violations of FIFO behavior

    • Example: Monitor the write and re...

  • Answered by AI
Interview experience
4
Good
Difficulty level
-
Process Duration
-
Result
-
Round 1 - Technical 

(2 Questions)

  • Q1. Basic question of sv like swapping no.
  • Q2. Question from projects
Interview experience
5
Excellent
Difficulty level
-
Process Duration
-
Result
-
Round 1 - One-on-one 

(2 Questions)

  • Q1. Assertions and coverage
  • Q2. Umv basic principle
  • Ans. 

    UVM (Universal Verification Methodology) basic principle is to provide a standardized methodology for verifying digital designs.

    • UVM is based on SystemVerilog and provides a framework for creating reusable verification environments

    • It promotes the use of object-oriented programming techniques for creating modular and scalable testbenches

    • UVM encourages the use of constrained-random stimulus generation and coverage-driven ...

  • Answered by AI

Interview Preparation Tips

Interview preparation tips for other job seekers - Prepare basics
Interview experience
4
Good
Difficulty level
-
Process Duration
-
Result
-
Round 1 - Technical 

(1 Question)

  • Q1. They asked from Digital, COA
Round 2 - Technical 

(1 Question)

  • Q1. They asked the concepts of COA
Round 3 - HR 

(1 Question)

  • Q1. First started with Puzzle and then about company
Interview experience
3
Average
Difficulty level
Moderate
Process Duration
2-4 weeks
Result
Not Selected

I applied via Campus Placement and was interviewed in Jan 2024. There was 1 interview round.

Round 1 - Technical 

(2 Questions)

  • Q1. Basics of analog , digital and vlsi
  • Q2. On face to face interview, they asked me abt my projects , digital, little analog , vlsi ( verilog), microcontrollers and c programming

Interview Preparation Tips

Interview preparation tips for other job seekers - Prepare well on your basics
Interview experience
4
Good
Difficulty level
Moderate
Process Duration
Less than 2 weeks
Result
Not Selected

I applied via LinkedIn and was interviewed in Oct 2023. There were 2 interview rounds.

Round 1 - Aptitude Test 

40 aptitude qns and some mcqs on basic programming

Round 2 - Technical 

(4 Questions)

  • Q1. I was asked to write two sum, palindrome function and merge sort code in whatever language I'm comfortable in
  • Q2. Two sum- return true or false
  • Ans. 

    Given an array of integers, determine if there are two numbers that add up to a specific target.

    • Iterate through the array and store each element in a hash set.

    • For each element, check if the difference between the target and the element exists in the hash set.

    • If the difference exists, return true; otherwise, continue iterating.

    • Example: nums = [2, 7, 11, 15], target = 9. The function should return true as 2 + 7 = 9.

  • Answered by AI
  • Q3. Merge sort function code
  • Q4. Palindromic string or not

Skills evaluated in this interview

Synopsys Interview FAQs

How many rounds are there in Synopsys Asic Design Verification Engineer interview?
Synopsys interview process usually has 2 rounds. The most common rounds in the Synopsys interview process are Technical, Aptitude Test and HR.
What are the top questions asked in Synopsys Asic Design Verification Engineer interview?

Some of the top questions asked at the Synopsys Asic Design Verification Engineer interview -

  1. Verilog coding A 100hz square wave signal 50 percent duty cycle is given Write...read more
  2. Why do you want to work at Synops...read more
  3. Basic digital like difference between latch and flipflop,Moore vs mealey which ...read more

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Synopsys Asic Design Verification Engineer Interview Process

based on 1 interview

Interview experience

5
  
Excellent
View more

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₹12 L/yr - ₹24 L/yr
72% more than the average Asic Design Verification Engineer Salary in India
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