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I want to work at Synopsys because of their reputation for innovation and cutting-edge technology in the field of ASIC design verification.
Synopsys is a leader in the EDA industry, known for their advanced tools and solutions for semiconductor design.
I am impressed by Synopsys' commitment to research and development, which aligns with my passion for pushing the boundaries of technology.
I believe working at Synopsys wil...
I applied via Campus Placement and was interviewed in Oct 2021. There were 3 interview rounds.
3 sections in exam
Aptitude,digital and verilog
Gate previous year will do for digital
Verilog code to divide frequency of a 100hz square wave signal with 50% duty cycle by 3.
Create a counter that counts up to 3 and resets back to 0
Use the counter to toggle an output signal every 3 cycles of the input signal
The output signal will have a frequency of 100/3 = 33.33hz with 50% duty cycle
posted on 18 Mar 2024
I applied via campus placement at Indian Institute of Technology (IIT), Kanpur and was interviewed before Mar 2023. There was 1 interview round.
A multiplexer (mux) is a digital circuit that selects one of several input signals and forwards it to a single output. A flip-flop (ff) is a type of latch circuit that stores a single bit of data.
Mux design involves selecting one of multiple input signals based on a control signal
FF design involves storing a single bit of data using a clock signal
Mux can be implemented using logic gates like AND, OR, and NOT gates
FF ca...
posted on 29 Nov 2024
Toggle the bits of given input
Create a mask with all bits set to 1
XOR the input with the mask to toggle the bits
Repeat the process for each bit position
Print a star pattern using loops
Use nested loops to print the desired pattern
Increment the number of stars in each row to create the pattern
Example: for a pattern with 5 rows - * , ** , *** , **** , *****
posted on 15 Jan 2025
A FIFO checker is a verification component used to monitor and validate the behavior of a First-In-First-Out buffer in a design.
Implement a monitor that tracks the input and output operations of the FIFO buffer
Check that the data is read out in the same order it was written in
Verify that the FIFO buffer does not overflow or underflow
Use assertions to flag any violations of FIFO behavior
Example: Monitor the write and re...
posted on 29 Aug 2024
UVM (Universal Verification Methodology) basic principle is to provide a standardized methodology for verifying digital designs.
UVM is based on SystemVerilog and provides a framework for creating reusable verification environments
It promotes the use of object-oriented programming techniques for creating modular and scalable testbenches
UVM encourages the use of constrained-random stimulus generation and coverage-driven ...
posted on 23 May 2024
posted on 29 Feb 2024
I applied via Campus Placement and was interviewed in Jan 2024. There was 1 interview round.
I applied via LinkedIn and was interviewed in Oct 2023. There were 2 interview rounds.
40 aptitude qns and some mcqs on basic programming
Given an array of integers, determine if there are two numbers that add up to a specific target.
Iterate through the array and store each element in a hash set.
For each element, check if the difference between the target and the element exists in the hash set.
If the difference exists, return true; otherwise, continue iterating.
Example: nums = [2, 7, 11, 15], target = 9. The function should return true as 2 + 7 = 9.
Some of the top questions asked at the Synopsys Asic Design Verification Engineer interview -
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