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Synopsys Asic Design Verification Engineer Interview Questions and Answers

Updated 23 Apr 2022

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Asic Design Verification Engineer Interview Questions

user image Anonymous

posted on 23 Apr 2022

I applied via Campus Placement and was interviewed in Oct 2021.

3 Interview Rounds

1

Aptitude Test Round

3 sections in exam
Aptitude,digital and verilog
Gate previous year will do for digital

2

Technical Round (1 Question)

  • Q1. Basic digital like difference between latch and flipflop,Moore vs mealey which one is better
    Add Answer
3

Technical Round (1 Question)

  • Q1. Verilog coding A 100hz square wave signal 50 percent duty cycle is given Write verilog code for dividing frequency of signal by 3.
    View Answers (2)

Interview Preparation Tips

Interview preparation tips for other job seekers - Be strong in verilog and be little thorough with what you did in internship

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2w
a technical project manager
Deadend
Hi, I'm here to share a part of my journey from the past 12 years in my career, I started from a package of 3.6LPA in 2013 at iGate and due to a few bad decisions on my career and worthless advices from people who are always pessimistic about the industry, I switched two companies and landed in a start-up with 2.4LPA. I worked hard nearly 8-16hrs a day single handed researched, built and managed an entire vertical of a project for 8 years. When the company didn't value my contribution and thought I was too young to become a manager, I had a package of 6LPA and Senior developer in designation. I switched for obvious reasons to a TL role for 12LPA and now at the same company I'm a TPM on the basis of my contribution with 48LPA as a fixed component. I feel outclassed in terms of having a fancy CV with certifications, I feel like CTC has hit a peak with 48LPA being fixed and nearly 40% in Variable. Most companies are hesitant to hire me because of this. What should be my next move?
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Interview questions from similar companies

Embedded Systems Engineer Interview Questions

Visteon user image Anonymous

posted on 16 Oct 2021

I applied via Referral and was interviewed in Apr 2021.

3 Interview Rounds

Interview Questions

Interview Preparation Tips

Interview preparation tips for other job seekers - Narrate your experience in ordered way and focus more on what you know
More about working at Synopsys

Synopsys Interview FAQs

How many rounds are there in Synopsys Asic Design Verification Engineer interview?
Synopsys interview process usually has 3 rounds. The most common rounds in the Synopsys interview process are Technical and Aptitude Test.
What are the top questions asked in Synopsys Asic Design Verification Engineer interview?

Some of the top questions asked at the Synopsys Asic Design Verification Engineer interview -

  1. Verilog coding A 100hz square wave signal 50 percent duty cycle is given Write...read more
  2. Basic digital like difference between latch and flipflop,Moore vs mealey which ...read more

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Synopsys Asic Design Verification Engineer Salary
based on 13 salaries
₹12 L/yr - ₹24 L/yr
73% more than the average Asic Design Verification Engineer Salary in India
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