R&D Engineering, Sr Engineer (VIP verification)

• Experience: 3yrs to 7years
• Expertise in UVM and System Verilog
• Experience in verification IP modelling with knowledge of test case coding, scoreboard design, assertions, checkers & functional coverage.
• Involved & played a driving role in the development of reusable Verification environments for at least 2 verification projects using VMM/OVM/UVM methodologies.
• Protocol experience: Should have experience on UCIe/PCIe/CXL/Unipro/USB/MIPI/HDMI/Ethernet/DDR/LPDDR/HBM memory protocol

Job responsibilities:

• Able to contribute to the development of the VIP
• Responsible & can be relied on for review sign-off of VIP development and updates from a technical perspective including methodology and protocol functional prospective.
• Liaison with Architects/methodology experts to achieve resolutions on issues or driving output from an architecture/methodology perspective.
• Locally should be to be "go-to" person on all technical aspects of VIP