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As a CPU/Processor Nest Verification lead, you will play a pivotal role in the pre-silicon functional and performance verification of our cutting-edge chipsets. Your responsibilities will cover a spectrum of critical areas, including the cache/nest subsystem, interrupt, Fabric, memory hierarchy, and various on-silicon IP integral to our upcoming IBM Power Systems offerings. Leveraging state-of-the-art techniques, you will be at the forefront of simulating and validating the designs of these bespoke microprocessor-based systems and providing technical guidance to junior/mid-level engineers in the team.

Key Duties:
Verification Environment Ownership: Take charge of the verification environments for microprocessor components, contributing significantly to the identification of functional and performance issues before silicon production. Implement best practices and innovative methodologies to ensure robust and efficient verification processes.
Documentation and Communication: Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Communicate progress effectively, keeping team members and stakeholders informed of milestones achieved and potential challenges encountered. Lead the development of the verification plans, environment, testbenches and writing testcases for the Cache Coherency Transport Interconnect Fabric in IBM Server Processors.

Technical leadership : Providing Technical leadership to the senior/mid-level engineers who will be working closely with you.

Stakeholder management : Managing and influencing stakeholders technically, periodic update in status meeting/technical forums.

• Functional Verification Experience: 15+ years of extensive experience in functional verification of processors, demonstrating a deep understanding of verification methodologies and technically leading a large team.
• Computer Architecture Knowledge: Good understanding of computer architecture, including Processor core design specifications, Coherency and Cache Designs, Processor IO subsystem, Interrupt architecture, with expertise in at least any one of the above domains.
• Multi-processor Cache Coherency Transport Fabric : Experience in functional verification of system level Coherency Transport Network designs and ways to stress verify them.
• Strong programming skills: Proficiency in C++, Python scripting or similar languages.

• Experience with Hardware Description Languages (HDLs): Proficiency in hardware description languages like Verilog and VHDL and general computational logic design and verification concepts.
• Experience in System-Level Verification: Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design.
• Experience in specifying and developing the verification infrastructure for verifying processor based designs.
• Minimum one full life cycle experience of a processor/SoC verification flow with focus on Coherency Transport Interconnect/Fabric Verification.
• Knowledge of system-level architecture including buses like AXI/ACE/CHI, AMBA interconnects