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Engaged Employer
Synopsys
3.9
based on 355 Reviews
Company Overview
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Working at Synopsys
Company Summary
Synopsys provides comprehensive design solutions for silicon and systems, enhancing R&D capabilities in the semiconductor industry to fuel future innovation.
Overall Rating
3.9/5
based on 355 reviews
On-Par with
industry average
Highly rated for
Company culture, Job security, Work-life balance
Work Policy
Hybrid
67% employees reported
Monday to Friday
93% employees reported
Flexible timing
89% employees reported
No travel
72% employees reported
View detailed work policy
Top Employees Benefits
Job/Soft skill training
30 employees reported
Health insurance
30 employees reported
Cafeteria
25 employees reported
Free meal
17 employees reported
View all benefits
About Synopsys
Founded in1986 (39 yrs old)
India Employee Count1k-5k
Global Employee Count1 Lakh+
HeadquartersSunnyvale, California
Office Locations
Websitesynopsys.com
Primary Industry
Other Industries
Synopsys delivers trusted and comprehensive silicon to systems design solutions, from electronic design automation to silicon IP and system verification and validation. We partner closely with semiconductor and systems customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
Mission: To Power Innovation Today to Ignite the Ingenuity of Tomorrow
Synopsys Ratings
based on 355 reviews
Overall Rating
3.9/5
How AmbitionBox ratings work?
5
149
4
111
3
51
2
16
1
28
Category Ratings
3.9
Company culture
3.9
Job security
3.9
Work-life balance
3.8
Salary
3.7
Skill development
3.6
Work satisfaction
3.4
Promotions
Synopsys is rated 3.9 out of 5 stars on AmbitionBox, based on 355 company reviews.This rating reflects an average employee experience, indicating moderate satisfaction with the company’s work culture, benefits, and career growth opportunities. AmbitionBox gathers authentic employee reviews and ratings, making it a trusted platform for job seekers and employees in India.
Read more
Gender Based Ratings at Synopsys
based on 332 reviews
3.9
Rated by 79 Women
Rated 4.1 for Work-life balance and 4.1 for Job security
3.9
Rated by 253 Men
Rated 3.9 for Work-life balance and 3.9 for Company culture
Work Policy at Synopsys
based on 68 reviews in last 6 months
Hybrid
67%
Work from office
28%
Permanent work from home
5%
Synopsys Reviews
Top mentions in Synopsys Reviews
+ 5 more
Compare Synopsys with Similar Companies
 |  Change Company |  Change Company |  Change Company | |
|---|---|---|---|---|
Overall Rating | 3.9/5 based on 355 reviews | 4.0/5 based on 115 reviews | 4.0/5 based on 55 reviews | 4.0/5 based on 274 reviews |
Highly Rated for | Work-life balance Job security Company culture | Work-life balance Salary Job security | Job security Work-life balance Skill development | Company culture Work-life balance Job security |
Critically Rated for |  No critically rated category | No critically rated category | No critically rated category | No critically rated category |
Primary Work Policy | Hybrid 67% employees reported | Hybrid 61% employees reported | - | Hybrid 68% employees reported |
Rating by Women Employees | 3.9 Good rated by 79 women | 3.7 Good rated by 21 women | 3.7 Good rated by 10 women | 4.0 Good rated by 63 women |
Rating by Men Employees | 3.9 Good rated by 253 men | 4.0 Good rated by 87 men | 4.0 Good rated by 30 men | 4.0 Good rated by 192 men |
Job security | 3.9 Good | 3.9 Good | 4.5 Good | 4.0 Good |
View more
Synopsys Salaries
Synopsys salaries have received with an average score of 3.8 out of 5 by 355 employees.
R&D Engineer
(148 salaries)
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₹8.5 L/yr - ₹32 L/yr
Senior R&D Engineer
(100 salaries)
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₹15 L/yr - ₹40 L/yr
Staff Engineer
(92 salaries)
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₹22 L/yr - ₹58.6 L/yr
Security Consultant
(62 salaries)
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₹5.8 L/yr - ₹21.1 L/yr
Software Engineer
(61 salaries)
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₹5.4 L/yr - ₹21.2 L/yr
Applications Engineer
(58 salaries)
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₹11 L/yr - ₹25.6 L/yr
Senior Software Engineer
(55 salaries)
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₹14 L/yr - ₹37 L/yr
Senior Application Engineer
(45 salaries)
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₹16 L/yr - ₹37 L/yr
Research and Development Engineer 2
(40 salaries)
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₹13 L/yr - ₹22 L/yr
Senior Engineer
(38 salaries)
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₹13 L/yr - ₹36.6 L/yr
Synopsys Interview Questions
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Synopsys Jobs
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Synopsys News
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Speeding Down Memory Lane With Custom HBM
- The semiconductor industry is embracing custom High Bandwidth Memory (cHBM) to enhance system performance and efficiency, offering more control and flexibility to SoC designers.
- High Bandwidth Memory (HBM) has gained popularity due to its advantages in memory bandwidth, lower latency, and compact form factor, making it ideal for data centers and demanding applications.
- The HBM market is projected to grow significantly by 2033, driven by AI computing, and is expected to dominate over half of the total DRAM market.
- Custom HBM allows for the integration of base die functionality into a logic die, enabling closer coordination between memory and processor dies for optimized power, performance, and area.
- cHBM reduces interposer-induced delays and brings memory and processor dies closer together, enhancing flexibility for various applications like edge AI and compute farms.
- Challenges with cHBM involve considering the entire lifecycle and dealing with vendor-specific DRAM algorithms, as well as the need for comprehensive in-field testing and diagnostics.
- Successful deployment of cHBM requires collaboration among IP providers, DRAM vendors, SoC designers, and ATE companies to address complex testing and integration requirements.
- Selecting the right partner, like Synopsys, is crucial for successful cHBM adoption, with ongoing enhancements and improvements in SLM solutions to support cHBM deployment.
- Collaboration with industry partners is key to advancing cHBM adoption, with further developments expected in 2025 to accelerate the utilization of custom HBM technology.
Semiengineering | 11 Mar, 2025
Multi-Die Health And Reliability: UCIe Advances
- Multi-die designs are popular for integrating heterogeneous and homogenous dies but bring complexities in ensuring chip health and reliability throughout its lifecycle.
- Synopsys collaborated with TSMC to demonstrate UCIe (Universal Chiplet Interconnect Express) for two dies, showcasing the importance of monitoring and testing multi-die designs.
- High-speed communication in UCIe requires rigorous monitoring, testing, and repair to maintain signal integrity and overall health of interconnects.
- Challenges include narrow pitch, lack of DFT ports, signal integrity maintenance, redundancy, and environmental variability in multi-die designs.
- Synopsys' Monitoring, Test & Repair (MTR) IP solution offers mission mode signal integrity monitoring, BIST algorithms, cumulative repair, and HSAT functions.
- MTR IP can be used at individual die and multi-die levels, during power-on and mission modes, facilitating health checks across different lifecycle scenarios.
- At the Chiplet Summit, Synopsys demonstrated success of UCIe PHY IP on TSMC N3E, showcasing first-pass silicon success and die-to-die communication advances.
- The MTR IP solution provides interconnect reliability, test, and repair features between UCIe IPs, supporting monitor, test, debug, and repair capabilities.
- Synopsys aims to enhance semiconductor technology through robust multi-die designs with maximum manufacturing yield and reliability using their MTR IP solution.
- The solution offers a framework for monitoring, testing, and repairing die-to-die interconnects across all stages of the silicon lifecycle.
Semiengineering | 7 Mar, 2025
Chip Industry Week In Review
- Apple plans to invest over $500 billion in the U.S. by building a new server factory and expanding facilities across several states, including Arizona and Texas.
- NIST introduced a new cybersecurity framework for chip manufacturing to mitigate cyber threats.
- imec achieved more than 90% yield on 20nm pitch metal lines using high-NA EUV technology for chip production.
- SkyWater Technology is set to acquire Infineon's 200mm Fab 25 in Texas to enhance U.S. capacity for various nodes required for industrial and defense sectors.
- Arm unveiled its Armv9 edge AI platform tailored for IoT applications, capable of running AI models with more than 1 billion parameters on-device.
- Micron started shipping its DDR5 memory based on the 1γ (10nm-class) DRAM node.
- Amazon Web Services introduced a quantum computing chip using 'cat qubits' to lower quantum error correction costs.
- GlobalFoundries and MIT announced a research agreement focused on leveraging silicon photonics technology.
- ASM, NVIDIA, Navitas, Synopsys, SkyWater Technology, and Valens released financial updates.
- Advantest and Micronics Japan partnered to develop advanced semiconductor test solutions, while Western Digital and Sandisk completed their separation.
Semiengineering | 28 Feb, 2025
Synopsys shares gain on stronger-than-expected earnings forecast
- Synopsys Inc. shares gain over 2% after forecasting stronger-than-expected earnings growth for Q2 2025.
- Synopsis reported Q1 adjusted earnings per share of $3.03, exceeding analysts' expectations.
- The company's electronic design automation revenue increased in the quarter, driven by growing demand for its software.
- Synopsys expects Q2 adjusted earnings per share of $3.37 to $3.42 on revenue of $1.585 billion to $1.615 billion.
Siliconangle | 27 Feb, 2025
Speeding Up Computational Lithography With The Power And Parallelism Of GPUs
- The article discusses the growing demands of computational lithography, particularly in addressing image errors during the lithographic process for dense chip designs.
- Traditional optical proximity correction (OPC) and emerging inverse lithography technology (ILT) play crucial roles in optimizing etched features.
- ILT, although more flexible, requires substantial computational power, with a single mask often consuming over 10K CPU cores for multiple days.
- Recent collaborative efforts by NVIDIA, TSMC, and Synopsys have shown that GPUs can significantly accelerate lithography computations, achieving speedups of 40X over CPUs.
- Key transformations involved in moving lithography code from CPUs to GPUs include parallelizing image-based operations, recasting algorithms to pixel-based computations, and migrating non-GPU-friendly data structures.
- Experiments in 2020 demonstrated a 10X speedup on ILT simulation functions using GPUs, with subsequent work revealing that GPUs can accelerate various computations used for OPC and ILT.
- A new GPU lithography library co-developed by NVIDIA, TSMC, and Synopsys has shown speedups as high as 40X over CPUs for certain functions.
- Overall, the shift from CPUs to GPUs has led to a total runtime speedup of more than 15X for one ILT 'recipe,' reducing multi-day CPU runs to under one day using fewer parallel machines.
- Research, development, and deployment in computational lithography are ongoing, with advancements in AI machine learning and CPU+GPU co-optimization contributing to further improvements.
- The latest progress will be presented at the NVIDIA GTC conference in San Jose, California, on March 21, with Synopsys exhibiting in Booth #222 from March 18 to March 21.
- The article showcases how GPUs can leverage their power and parallelism to enhance computational lithography processes for semiconductor chip design.
Semiengineering | 20 Feb, 2025
Chip Industry Week In Review
- Worldwide silicon wafer shipments declined nearly 2.7% to 12,266 million square inches in 2024, with wafer revenue contracting 6.5% to $11.5 billion.
- CSIS released a new report focusing on building a secure mineral supply chain for semiconductors, particularly in refining gallium and germanium.
- Europe is investing significantly in AI infrastructure projects, with France announcing over €109 billion in investments and the EU Commission launching InvestAI initiative.
- Advantest introduced an ultra-high-speed DRAM test system for GDDR7, LPDDR6, and DDR6 applications in AI, HPC, and edge technologies.
- Synopsys expanded its hardware-assisted verification portfolio with new prototyping and emulation systems based on AMD's Versal adaptive SoC.
- Semiconductor Engineering delved into topics like signal integrity in chiplet design and multi-physics in the Low Power-High Performance newsletter.
- Lam Research, TSMC, and other companies in Asia and Europe made notable investments and collaborations in the semiconductor industry.
- NXP plans to acquire Kinara, Groq secures a $1.5 billion commitment, and other companies like EnCharge AI and Salience Labs receive significant funding.
- Yole Group and TrendForce provided insights on the semiconductor and AI server markets, with expectations of strong growth rates and challenges for 2025.
- Google Cloud shared solutions for power spikes in AI workloads, while advancements in quantum computing and supercomputing were also highlighted.
- Companies like Nordson, Siemens EDA, Infineon, and Ansys announced new products, collaborations, and achievements in various technology sectors.
Semiengineering | 14 Feb, 2025
Optimizing DFT With AI And BiST
- AI and machine learning are changing DFT strategies by optimizing architecture through smart technologies.
- AI can analyze designs, suggest DFT architecture improvements, and speed up design implementation.
- AI helps in ATPG pattern generation, reducing test time and cost by exploring optimal parameter combinations.
- Collaboration between design and test teams is crucial for effective DFT, ensuring seamless integration across design stages.
- Logic and memory BiST face challenges, with the need for adaptive and comprehensive end-to-end test solutions.
- In-system deterministic test patterns streamline testing processes, enabling detailed diagnosis without hardware removal in data center applications.
- Real-time data sharing, machine learning, and collaborative approaches enhance DFT capabilities and adaptability.
- Effective DFT strategies require observability, controllability principles, and continuous innovation to address complex design challenges.
- Power distribution, flexibility in architecture, and tailored testing approaches are critical considerations for efficient DFT.
- Improving fault coverage, optimizing test costs, and integrating advanced technologies are essential for achieving cost-effective DFT solutions.
Semiengineering | 12 Feb, 2025
Silent Data Errors Still Slipping Through The Cracks
- Silent data corruption errors in large server farms have become a major concern of cloud users, hyperscalers, processor manufacturers and the test community.
- Silent data errors (also called silent data corruption errors) are hardware errors that occur when an incorrect computational result from a processor core goes undetected by the system.
- Silent data errors are not a new type of failure or caused by a new type of defect, but they are more noticeable.
- Both Google and Meta sounded the alarm about SDC errors a few years ago, and the extent of the problem boils down to 1 in 1,000 machines in a data center fleet having a silent data error.
- These silent data errors also have become more prevalent due to ever-shrinking transistors fabricated near their physical limits, huge numbers of cores in data centers running identical code, and the limitations in testing hugely complex systems.
- Effective screening and testing can help to detect SDCs, both during fabrication and during field use.
- Stress testing is a powerful play here.
- Systems are likely to get more complex, so one key in dealing with SDEs may lie in developing more fault-tolerant systems with superior error correction mechanisms and built-in resiliency.
- ‘In the future, we’re going to be talking about reliability as a first-class design parameter in architectures,’ said Rambus’ Woo.
- And while it’s not clear that the industry will unravel all the root cause contributors to silent data errors, strategies to identify, check/verify, diagnose and test for SDEs are well underway.
Semiengineering | 11 Feb, 2025
Automotive Security Shifts To The System Level
- As the amount of semiconductor and software content continues to increase, so does the number of over-the-air updates and connections to edge-based servers and services, adding a variety of new vectors for attacks.
- Properly securing vehicles requires engineers to first identify all the possible connection points.
- In the strictest sense, there’s only one direct attack vector on a car, according to David Glasco, vice president for compute solutions group at Cadence — the WiFi through which all software updates are uploaded.
- The migration toward holistic security now includes roots of trust installed in ICs located throughout the car’s systems.
- “Security is just like safety,” he said. “Security is the ultimate. It is the top priority.
- The challenge for automakers is understanding how these systems of systems will behave both individually and together, and that may require security training as a pre-requisite for any facet of automotive design.
- SDVs are booming, but designing hardware that can run software updates a decade in the future is a huge challenge.
- The core of all security comes down to proper, strong cryptography.
- “Having multiple environments is very similar to having different privilege levels within the CPU structure, which allows you to assign a very low privilege, for example, to a third-party app,” he said.
- The international standard has been proven effective in automotive functional safety and has begun to spread to other markets.
Semiengineering | 6 Feb, 2025
Automotive Outlook 2025: Ecosystem Pivots Around SDV
- The automotive industry is shifting towards the software-defined vehicle architectures (SDV) that will change how automakers design, source, and use automotive chips.
- SDV provides various benefits to automakers because it can reduce manufacturing costs, upgrade the operational platform quickly, support scalability and flexibility, and deliver advanced user experience.
- SDV requires software-first development and a shift from the mechanical and hardware-centric point of view to software-centralized infrastructure that can build and integrate the hardware accordingly.
- This shift involves creating a zonal architecture with powerful central CPUs to consolidate electronic control units (ECUs) into fewer, more powerful platforms that centralize processing resources in vehicles.
- The zonal architecture enables the integration of advanced technologies such as AI and autonomous driving systems, and it simplifies the vehicle design process while reducing complexity, weight, and cost.
- Chip vendors are building multi-die licensable devices featuring multiple chips in a single package, allowing the creation of advanced products using advanced packages at 3nm and a range of chiplets from different vendors.
- SDV enhances AI use in the vehicle, delivering an advanced user experience that learns from driver behaviors and enhances automated driving systems with end-to-end self-supervised learning and advanced AI in the vehicle.
- Software-defined development speeds up the introduction of new technologies that OEMs and Tier Ones are embracing. However, OEMs and Tier Ones must adapt to software-first development with a focus on security since the distribution of software centrally intensifies security issues.
- SDV makes it possible to develop software independently within the cloud on servers and substantially reduces the development time and cost with a level of flexibility and scalability that traditional hardware development cannot match.
- Virtual platforms and virtual prototypes are accelerating the software and silicon development cycles, simultaneously designing the hardware and software, testing them for security, scalability, flocking everything together into a scalable E/E architecture for the whole car.
Semiengineering | 6 Feb, 2025
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Synopsys FAQs
When was Synopsys founded?
Synopsys was founded in 1986. The company has been operating for 39 years primarily in the Semiconductors sector.
Where is the Synopsys headquarters located?
Synopsys is headquartered in Sunnyvale, California. It operates in 3 cities such as Bangalore / Bengaluru, Noida, Hyderabad / Secunderabad. To explore all the office locations, visit Synopsys locations.
How many employees does Synopsys have in India?
Synopsys currently has more than 2,300+ employees in India. Engineering - Software & QA department appears to have the highest employee count in Synopsys based on the number of reviews submitted on AmbitionBox.
Does Synopsys have good work-life balance?
Synopsys has a Work-Life Balance Rating of 3.9 out of 5 based on 300+ employee reviews on AmbitionBox. 73% employees rated Synopsys 4 or above, while 27% employees rated it 3 or below on work-life balance. This indicates that the majority of employees feel a generally balanced work-life experience, with some opportunities for improvement based on the feedback. We encourage you to read Synopsys work-life balance reviews for more details
Is Synopsys good for career growth?
Career growth at Synopsys is rated as moderate, with a promotions and appraisal rating of 3.4. 27% employees rated Synopsys 3 or below, while 73% employees rated it 4 or above on promotions/appraisal. This rating suggests that while some employees view growth opportunities favorably, there is scope for improvement based on employee feedback. We recommend reading Synopsys promotions/appraisals reviews for more detailed insights.
What are the pros of working in Synopsys?
Working at Synopsys offers several advantages that make it an appealing place for employees. The company is highly rated for company culture, job security and work life balance, based on 300+ employee reviews on AmbitionBox.
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