Asic Design Verification Engineer
Asic Design Verification Engineer Interview Questions and Answers
Q1. Verilog coding A 100hz square wave signal 50 percent duty cycle is given Write verilog code for dividing frequency of signal by 3.
Verilog code to divide frequency of a 100hz square wave signal with 50% duty cycle by 3.
Create a counter that counts up to 3 and resets back to 0
Use the counter to toggle an output signal every 3 cycles of the input signal
The output signal will have a frequency of 100/3 = 33.33hz with 50% duty cycle
Q2. how to predict if a 32 bit number is divisible by 8, draw a circuit using gates
To predict if a 32 bit number is divisible by 8, design a circuit using gates.
Use a circuit with AND, OR, and NOT gates to check if the last three bits of the number are all zeros.
If the last three bits are zeros, then the number is divisible by 8.
For example, if the 32 bit number is 11010000, the last three bits are zeros, so it is divisible by 8.
Asic Design Verification Engineer Interview Questions and Answers for Freshers
Q3. Conversation one number system to other. Make nand gate using Mux.
Convert number system by dividing by base and taking remainders. Use 2:1 Mux to implement NAND gate.
To convert from one number system to another, divide by the base of the original system and take remainders.
For example, to convert decimal 10 to binary, repeatedly divide by 2 and take remainders: 10/2=5 R0, 5/2=2 R1, 2/2=1 R0, 1/2=0 R1. So, 10 in decimal is 1010 in binary.
To implement a NAND gate using a 2:1 Mux, connect one input to the select line and the other input to the...read more
Q4. Whats a bus functional model and how it's written
A bus functional model is a high-level model of a bus protocol used for verification. It is written in a hardware description language.
A bus functional model simulates the behavior of a bus protocol in a verification environment.
It is written in a hardware description language like SystemVerilog or VHDL.
The model includes the functionality of the bus protocol such as transactions, timing, and error handling.
It is used to verify the interaction between the design under test an...read more
Q5. Why do you want to work at Synopsys?
I want to work at Synopsys because of their reputation for innovation and cutting-edge technology in the field of ASIC design verification.
Synopsys is a leader in the EDA industry, known for their advanced tools and solutions for semiconductor design.
I am impressed by Synopsys' commitment to research and development, which aligns with my passion for pushing the boundaries of technology.
I believe working at Synopsys will provide me with valuable experience and opportunities fo...read more
Q6. Write a 8X1 mux using if else with clock and reset
Implementing an 8X1 mux using if else statements with clock and reset
Declare input signals, output signal, clock and reset signals
Use if else statements to select the output based on the select lines
Ensure proper handling of clock and reset signals
Example: if(sel == 3) output = in3;
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Q7. What is inheritance
Inheritance is a concept in object-oriented programming where a class inherits attributes and methods from another class.
Allows a class to inherit attributes and methods from another class
Promotes code reusability and reduces redundancy
Creates a parent-child relationship between classes
Derived class can override or extend the functionality of the base class
Example: Class 'Car' can inherit from class 'Vehicle' to reuse common attributes like 'color' and 'speed'
Q8. What is polymorphism
Polymorphism is the ability of a function or method to behave differently based on the object it is called with.
Polymorphism allows objects of different classes to be treated as objects of a common superclass.
It enables a single interface to represent multiple data types.
Examples include method overloading and method overriding in object-oriented programming languages like Java.
Asic Design Verification Engineer Jobs
Q9. design of mux and ff
A multiplexer (mux) is a digital circuit that selects one of several input signals and forwards it to a single output. A flip-flop (ff) is a type of latch circuit that stores a single bit of data.
Mux design involves selecting one of multiple input signals based on a control signal
FF design involves storing a single bit of data using a clock signal
Mux can be implemented using logic gates like AND, OR, and NOT gates
FF can be implemented using basic components like NAND gates
Bot...read more
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