Asic Design Verification Engineer
Asic Design Verification Engineer Interview Questions and Answers for Freshers
Q1. Verilog coding A 100hz square wave signal 50 percent duty cycle is given Write verilog code for dividing frequency of signal by 3.
Verilog code to divide frequency of a 100hz square wave signal with 50% duty cycle by 3.
Create a counter that counts up to 3 and resets back to 0
Use the counter to toggle an output signal every 3 cycles of the input signal
The output signal will have a frequency of 100/3 = 33.33hz with 50% duty cycle
Q2. Conversation one number system to other. Make nand gate using Mux.
Convert number system by dividing by base and taking remainders. Use 2:1 Mux to implement NAND gate.
To convert from one number system to another, divide by the base of the original system and take remainders.
For example, to convert decimal 10 to binary, repeatedly divide by 2 and take remainders: 10/2=5 R0, 5/2=2 R1, 2/2=1 R0, 1/2=0 R1. So, 10 in decimal is 1010 in binary.
To implement a NAND gate using a 2:1 Mux, connect one input to the select line and the other input to the...read more
Asic Design Verification Engineer Jobs
Interview experiences of popular companies
Calculate your in-hand salary
Confused about how your in-hand salary is calculated? Enter your annual salary (CTC) and get your in-hand salary
Reviews
Interviews
Salaries
Users/Month