Upload Button Icon Add office photos
Engaged Employer

i

This company page is being actively managed by Synopsys Team. If you also belong to the team, you can get access from here

Synopsys Verified Tick

Compare button icon Compare button icon Compare

Filter interviews by

Synopsys VLSI Design and Verification Engineer Interview Questions and Answers

Updated 20 Mar 2024

Synopsys VLSI Design and Verification Engineer Interview Experiences

2 interviews found

Interview experience
4
Good
Difficulty level
-
Process Duration
-
Result
No response
Round 1 - Technical 

(2 Questions)

  • Q1. What is setup time ?
  • Ans. 

    Setup time is the amount of time a data input signal must be stable before the clock edge for proper operation of a flip-flop.

    • Setup time is the minimum time required for the input data signal to be stable before the clock edge.

    • It ensures that the data input is captured correctly by the flip-flop.

    • If the setup time is not met, the flip-flop may capture the wrong data.

    • Setup time violations can lead to timing issues in dig...

  • Answered by AI
  • Q2. 3 input xor and xnor gate

Interview Preparation Tips

Interview preparation tips for other job seekers - Good to go

Skills evaluated in this interview

I applied via campus placement at B M S College of Engineering, Bangalore and was interviewed in Jun 2022. There were 3 interview rounds.

Round 1 - Resume Shortlist 
Pro Tip by AmbitionBox:
Keep your resume crisp and to the point. A recruiter looks at your resume for an average of 6 seconds, make sure to leave the best impression.
View all tips
Round 2 - Aptitude Test 

50 questions for 90 mins

Round 3 - Technical 

(1 Question)

  • Q1. Basic digital electronics ,static time analysis, verilog coding , basic c programing

Interview Preparation Tips

Interview preparation tips for other job seekers - focus on digital and verilog and go through gate paper for aptitude round

VLSI Design and Verification Engineer Interview Questions Asked at Other Companies

Q1. How many combinations of inverter can be made using just 1 nand g ... read more
Q2. what is ring counter, Jhonson counter, Sync and Async Counters.
Q3. Difference between Bocking and Non-Blocking in Verilog
Q4. What do you mean by universal Gates?
Q5. using 2:1 mux make inverter, AND Gate, OR Gate.

Interview questions from similar companies

Interview experience
4
Good
Difficulty level
-
Process Duration
-
Result
-
Round 1 - Technical 

(2 Questions)

  • Q1. Basic question of sv like swapping no.
  • Q2. Question from projects
Interview experience
5
Excellent
Difficulty level
-
Process Duration
-
Result
-
Round 1 - One-on-one 

(2 Questions)

  • Q1. Assertions and coverage
  • Q2. Umv basic principle
  • Ans. 

    UVM (Universal Verification Methodology) basic principle is to provide a standardized methodology for verifying digital designs.

    • UVM is based on SystemVerilog and provides a framework for creating reusable verification environments

    • It promotes the use of object-oriented programming techniques for creating modular and scalable testbenches

    • UVM encourages the use of constrained-random stimulus generation and coverage-driven ...

  • Answered by AI

Interview Preparation Tips

Interview preparation tips for other job seekers - Prepare basics
Interview experience
4
Good
Difficulty level
-
Process Duration
-
Result
-
Round 1 - Technical 

(1 Question)

  • Q1. They asked from Digital, COA
Round 2 - Technical 

(1 Question)

  • Q1. They asked the concepts of COA
Round 3 - HR 

(1 Question)

  • Q1. First started with Puzzle and then about company
Interview experience
5
Excellent
Difficulty level
Moderate
Process Duration
-
Result
-

I applied via Referral and was interviewed in Apr 2024. There was 1 interview round.

Round 1 - Technical 

(2 Questions)

  • Q1. Simple FSM given similar to mux and asked for testcases and assertions.
  • Q2. Coverage to write transitions of states.
  • Ans. 

    Coverage-driven verification techniques are used to ensure all possible state transitions are exercised.

    • Coverage metrics like state, transition, and toggle coverage can be used to track the completeness of state transitions.

    • Writing directed tests to cover specific state transitions can help achieve higher coverage.

    • Random stimulus generation can also be used to explore different state transitions.

    • Functional coverage can...

  • Answered by AI
Interview experience
3
Average
Difficulty level
Moderate
Process Duration
2-4 weeks
Result
Not Selected

I applied via Campus Placement and was interviewed in Jan 2024. There was 1 interview round.

Round 1 - Technical 

(2 Questions)

  • Q1. Basics of analog , digital and vlsi
  • Q2. On face to face interview, they asked me abt my projects , digital, little analog , vlsi ( verilog), microcontrollers and c programming

Interview Preparation Tips

Interview preparation tips for other job seekers - Prepare well on your basics
Interview experience
4
Good
Difficulty level
-
Process Duration
-
Result
-
Round 1 - Technical 

(1 Question)

  • Q1. The question was draw cmos inverter transfer characteristics and by varying some parameters they asked their effects on it.
Interview experience
4
Good
Difficulty level
Moderate
Process Duration
2-4 weeks
Result
-

I applied via Company Website and was interviewed in Jan 2023. There were 2 interview rounds.

Round 1 - Resume Shortlist 
Pro Tip by AmbitionBox:
Keep your resume crisp and to the point. A recruiter looks at your resume for an average of 6 seconds, make sure to leave the best impression.
View all tips
Round 2 - Technical 

(2 Questions)

  • Q1. Computer architecture UVM SV Constraints
  • Q2. Fibonacci series constraints

Interview Preparation Tips

Interview preparation tips for other job seekers - Prepare one project well
Prepare uvm system verilog
code constraints
Round 1 - Resume Shortlist 
Pro Tip by AmbitionBox:
Don’t add your photo or details such as gender, age, and address in your resume. These details do not add any value.
View all tips
Round 2 - Aptitude Test 

Verilog, c++ pointers, mosfets

Round 3 - Technical 

(3 Questions)

  • Q1. In depth questions about coding language you chose?
  • Ans. Use pointers to solve a problem
  • Answered Anonymously
  • Q2. Use uart protocol to solve a problem?
  • Ans. 

    UART protocol can be used to transmit and receive data between two devices.

    • UART can be used to communicate between a microcontroller and a computer

    • UART can be used to send and receive data between two microcontrollers

    • UART can be used to interface with sensors and actuators

    • UART can be used to implement a simple command/response protocol

    • UART can be used to implement a data logging system

  • Answered by AI
  • Q3. Use uart to receive signals from micrcontroller
  • Ans. 

    UART can be used to receive signals from a microcontroller.

    • Connect the UART pins of the microcontroller to the UART pins of the receiving device.

    • Configure the UART settings such as baud rate, parity, and stop bits.

    • Use a UART library or write code to read the incoming data from the UART buffer.

    • Process the received data as required by the application.

  • Answered by AI

Interview Preparation Tips

Interview preparation tips for other job seekers - be confident, say i dont know if you really dont know

Skills evaluated in this interview

Synopsys Interview FAQs

How many rounds are there in Synopsys VLSI Design and Verification Engineer interview?
Synopsys interview process usually has 2 rounds. The most common rounds in the Synopsys interview process are Technical, Resume Shortlist and Aptitude Test.
What are the top questions asked in Synopsys VLSI Design and Verification Engineer interview?

Some of the top questions asked at the Synopsys VLSI Design and Verification Engineer interview -

  1. What is setup tim...read more
  2. basic digital electronics ,static time analysis, verilog coding , basic c progr...read more
  3. 3 input xor and xnor g...read more

Tell us how to improve this page.

Synopsys VLSI Design and Verification Engineer Interview Process

based on 1 interview

Interview experience

4
  
Good
View more

Interview Questions from Similar Companies

Intel Interview Questions
4.2
 • 214 Interviews
Texas Instruments Interview Questions
4.1
 • 120 Interviews
Molex Interview Questions
3.9
 • 53 Interviews
Lam Research Interview Questions
3.7
 • 44 Interviews
View all
R&D Engineer
148 salaries
unlock blur

₹7.3 L/yr - ₹32 L/yr

Senior R&D Engineer
99 salaries
unlock blur

₹15 L/yr - ₹40 L/yr

Staff Engineer
88 salaries
unlock blur

₹22 L/yr - ₹45.5 L/yr

Security Consultant
60 salaries
unlock blur

₹5.8 L/yr - ₹21 L/yr

Applications Engineer
58 salaries
unlock blur

₹11 L/yr - ₹25.6 L/yr

Explore more salaries
Compare Synopsys with

Cadence Design Systems

4.1
Compare

Mentor Graphics

4.0
Compare

Ansys Software Private Limited

3.9
Compare

Infineon Technologies

3.9
Compare
Did you find this page helpful?
Yes No
write
Share an Interview