Micron Technology Asic Design Verification Engineer Interview Questions and Answers

Q1. Design of mux and ff
Ans. 
A multiplexer (mux) is a digital circuit that selects one of several input signals and forwards it to a single output. A flip-flop (ff) is a type of latch circuit that stores a single bit of data.
• Mux design involves selecting one of multiple input signals based on a control signal

• FF design involves storing a single bit of data using a clock signal

• Mux can be implemented using logic gates like AND, OR, and NOT gates

• FF ca...read more
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Q2. Basics of sv n verilog
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Q3. Sta question about timing violation
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Q4. Thesis related question
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Q5. Some basic design question
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Q1. What is cross talk
Ans. 
Cross talk is the unwanted transfer of signals between different components or traces on a circuit board.
• Occurs when signals from one trace interfere with signals on another trace

• Can lead to signal distortion or errors in data transmission

• Prevented by proper spacing and shielding between traces

• Example: Cross talk between data lines on a PCB causing errors in communication
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Q2. How to define generated clocks through edges
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Generated clocks through edges are defined by specifying the source clock and the edge on which the generated clock is based.
• Specify the source clock for the generated clock

• Define the edge (rising/falling) on which the generated clock is based

• Use tools like Synopsys Design Compiler to define generated clocks
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Q1. Assertions and coverage
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Q2. Umv basic principle
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UVM (Universal Verification Methodology) basic principle is to provide a standardized methodology for verifying digital designs.
• UVM is based on SystemVerilog and provides a framework for creating reusable verification environments

• It promotes the use of object-oriented programming techniques for creating modular and scalable testbenches

• UVM encourages the use of constrained-random stimulus generation and coverage-driven ...read more
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Q1. Basics of analog , digital and vlsi
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Q2. On face to face interview, they asked me abt my projects , digital, little analog , vlsi ( verilog), microcontrollers and c programming
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Q1. Is setup and hold uncertainty values are different
Ans. 
Yes, setup and hold uncertainty values are different in physical design engineering.
• Setup uncertainty is related to the arrival time of the data signal at the input of the flip-flop, while hold uncertainty is related to the removal time of the data signal.

• Setup time is the minimum amount of time the data input must be stable before the clock edge, while hold time is the minimum amount of time the data input must be sta...read more
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3 sections in exam
Aptitude,digital and verilog
Gate previous year will do for digital

Q1. Basic digital like difference between latch and flipflop,Moore vs mealey which one is better
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Q1. Verilog coding A 100hz square wave signal 50 percent duty cycle is given Write verilog code for dividing frequency of signal by 3.
Ans. 
Verilog code to divide frequency of a 100hz square wave signal with 50% duty cycle by 3.
• Create a counter that counts up to 3 and resets back to 0

• Use the counter to toggle an output signal every 3 cycles of the input signal

• The output signal will have a frequency of 100/3 = 33.33hz with 50% duty cycle
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40 aptitude qns and some mcqs on basic programming

Q1. I was asked to write two sum, palindrome function and merge sort code in whatever language I'm comfortable in
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Q2. Two sum- return true or false
Ans. 
Given an array of integers, determine if there are two numbers that add up to a specific target.
• Iterate through the array and store each element in a hash set.

• For each element, check if the difference between the target and the element exists in the hash set.

• If the difference exists, return true; otherwise, continue iterating.

• Example: nums = [2, 7, 11, 15], target = 9. The function should return true as 2 + 7 = 9.
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Q3. Merge sort function code
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Q4. Palindromic string or not
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