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AumRaj Design Systems
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AumRaj Design Systems Asic Design Verification Engineer Interview Questions and Answers
AumRaj Design Systems Asic Design Verification Engineer Interview Experiences
1 interview found
I applied via LinkedIn and was interviewed in Jun 2023. There were 4 interview rounds.
Group discussion on mainly digital, verilog, system verilog. Was approx 2 hours.
Same as first round some 50% questions are repeated from first round. Was approx 2 hours
(2 Questions)
- Q1. Questions on digital, write code for counter in verilog, some logical Questions
- Q2. Conversation one number system to other. Make nand gate using Mux.
- Ans.
Convert number system by dividing by base and taking remainders. Use 2:1 Mux to implement NAND gate.
To convert from one number system to another, divide by the base of the original system and take remainders.
For example, to convert decimal 10 to binary, repeatedly divide by 2 and take remainders: 10/2=5 R0, 5/2=2 R1, 2/2=1 R0, 1/2=0 R1. So, 10 in decimal is 1010 in binary.
To implement a NAND gate using a 2:1 Mux, conne...
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After clearing 3 rounds they didn't select. Don't know why .
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Selected
I applied via Referral and was interviewed in Dec 2023. There were 4 interview rounds.
They need fewer people in less salary, so don't waste your time.
Electronic question.
Hr interviews with basic questions
(2 Questions)
- Q1. Fhhh ffhjj fjfj gjj
- Q2. Dhh ffhhh fjfj fjjfj
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Selected
I appeared for an interview before Feb 2024.
(1 Question)
- Q1. Salary negotiation
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I applied via Referral and was interviewed before Sep 2020. There was 1 interview round.
Interview Questionnaire
2 Questions
- Q1. Basic c programming
- Q2. Previous experience questions
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Senior Engineer Interview Questions & Answers
Renesas Electronics India
Anonymous
posted on 8 Jul 2021
Interview Questionnaire
1 Question
- Q1. State machines
Senior Engineer Interview Questions & Answers
Smiiel - A Unit Of Motherson Sumi System
Anonymous
posted on 14 Jan 2022
I applied via Referral and was interviewed before Jan 2021. There were 3 interview rounds.
Interview Questionnaire
1 Question
- Q1. Your Introduction
Interview Preparation Tips
I applied via Campus Placement and was interviewed in Dec 2016. There were 5 interview rounds.
Interview Questionnaire
2 Questions
- Q1. Communication Concepts
- Q2. Embedded Concepts
Interview Preparation Tips
Experience: Shortlisted based on CGPA and Profile
Tips: CGPA above 7.5 and Communication/CS based coursework/ability
Round: Test
Experience: C Coding Questions which checked basic knowledge of C
Tips: Brush up your C skills. Questions are easy but may require knowledge of stuff like what is big endian and little endian etc.
Duration: 1 hour 30 minutes
Total Questions: 12
Round: Technical Interview
Experience: My Communication relation concepts were tested. My Major Project was asked in detail.
Tips: If Comm background, prepare ITC, MultiCarrier/Wireless at a good level. If not they will ask C.
Round: Technical Interview
Experience: I was asked basic level embedded concepts.
Tips: Prepare on the following and similar stuff : How to implement a pseudo dynamic memory allocation using flash memory- which data structure to use. How does Inter Process Communication work. How does a multicore processor synchronizes its cores. If Comm background, give the TX and RX chain design (Wireless System Design)
Skills: Communication Systems, Embedded Systems, C Programming
College Name: IIT Madras
Gayathri S ee15m052
I applied via Campus Placement and was interviewed before Dec 2015. There were 2 interview rounds.
Interview Preparation Tips
Experience: It was a written test with some numerical aptitude questions and coding questions. The test was fairly easy
Duration: 1 hour
College Name: IIT Madras
I applied via Campus Placement and was interviewed in Dec 2016. There were 3 interview rounds.
Interview Preparation Tips
Experience: It was a written test with some numerical aptitude questions and coding questions. The test was fairly easy
Tips: Learn about pointers and using function pointers
Round: Technical Interview
Experience: First, I was asked to brief about the projects I have done so far. Then there were some questions about C programming like pointers, const pointers, storage classes, volatile keyword etc. It was followed by some basic questions about computer architecture, microcontroller, FPGA, RTOS
Round: Technical Interview
Experience: In this round I was asked to write algorithm for some simple problems like checking if a given integer (not string) is palindrome or not, checking if a number is a multiple of 3 (using bitwise operations) etc
College Name: IIT Madras
Senior Engineer Interview Questions & Answers
Smiiel - A Unit Of Motherson Sumi System
posted on 11 Jun 2022
(1 Question)
- Q1. In which face we develop PPAP documents
- Ans.
PPAP documents are developed in the Production Part Approval Process (PPAP) face.
PPAP documents are developed during the production part approval process.
This is typically the fourth phase of the APQP (Advanced Product Quality Planning) process.
PPAP documents include items such as control plans, FMEAs, and measurement system analysis.
The purpose of PPAP is to ensure that all parts meet customer requirements and specifi...
(1 Question)
- Q1. What is the shrinkage value of pa66
- Ans.
The shrinkage value of pa66 varies depending on the specific grade and processing conditions.
Shrinkage is the reduction in size of a molded part as it cools and solidifies.
The shrinkage value of pa66 can range from 1.5% to 3.5%.
Factors that affect shrinkage include mold design, processing parameters, and part geometry.
It is important to account for shrinkage when designing molds and parts to ensure proper fit and funct
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AumRaj Design Systems Asic Design Verification Engineer Interview Process
based on 1 interview
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AumRaj Design Systems Asic Design Verification Engineer Reviews and Ratings
based on 2 reviews
Rating in categories
|
Design & Verification Engineer
4
salaries
|  ₹12 L/yr - ₹15 L/yr |
|
Embedded Firmware Engineer
4
salaries
| ₹2 L/yr - ₹10.2 L/yr |
|
Senior Embedded Hardware Design Engineer
4
salaries
| ₹13.2 L/yr - ₹24.1 L/yr |
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