Upload Button Icon Add office photos
Engaged Employer

i

This company page is being actively managed by Synopsys Team. If you also belong to the team, you can get access from here

Synopsys Verified Tick

Compare button icon Compare button icon Compare

Filter interviews by

Clear (1)

Synopsys RTL Design and Verification Engineer Interview Questions and Answers

Updated 24 Oct 2024

Synopsys RTL Design and Verification Engineer Interview Experiences

1 interview found

Interview experience
3
Average
Difficulty level
Moderate
Process Duration
2-4 weeks
Result
Not Selected

I applied via Campus Placement and was interviewed in Apr 2024. There were 2 interview rounds.

Round 1 - Aptitude Test 

It was easy and basic

Round 2 - Technical 

(2 Questions)

  • Q1. Questions about verilog
  • Q2. Difference between task and function
  • Ans. 

    Task is used for sequential execution while function is used for parallel execution.

    • Task is used for modeling sequential behavior in Verilog/SystemVerilog

    • Function is used for modeling combinational logic in Verilog/SystemVerilog

    • Task can contain delays and blocking statements

    • Function cannot contain delays or blocking statements

  • Answered by AI

Interview questions from similar companies

I applied via Referral

Interview Questionnaire 

35 Questions

  • Q1. Tell me something about yourself
  • Ans. 

    I am a physical design engineer with experience in designing and optimizing integrated circuits.

    • I have a Bachelor's degree in Electrical Engineering

    • I have worked on multiple projects involving ASIC design and verification

    • I am proficient in using industry-standard EDA tools such as Cadence and Synopsys

    • I have experience in optimizing power, area, and timing constraints for ICs

    • I am a team player and have collaborated with...

  • Answered by AI
  • Q2. Can you explain more about your project, What was your role in it ?
  • Ans. 

    I worked on a project involving physical design of a microprocessor chip.

    • My role was to design and optimize the layout of the chip using industry-standard EDA tools.

    • I collaborated with the design team to ensure that the chip met performance and power requirements.

    • I also performed timing analysis and physical verification to ensure that the chip was manufacturable.

    • The project involved working with advanced process nodes...

  • Answered by AI
  • Q3. Which is the subject you like the most?
  • Ans. 

    I enjoy studying computer architecture and digital logic design.

    • Computer architecture

    • Digital logic design

    • Microprocessor design

    • VLSI design

  • Answered by AI
  • Q4. Can you draw a CMOS inverter and explain
  • Ans. 

    A CMOS inverter is a digital logic gate that converts a digital input signal to its complement.

    • It consists of a PMOS transistor and an NMOS transistor connected in series.

    • The input signal is connected to the gates of both transistors.

    • The output is taken from the drain of the PMOS transistor and the drain of the NMOS transistor.

    • When the input is high, the PMOS transistor is off and the NMOS transistor is on, resulting i...

  • Answered by AI
  • Q5. Can you explain 5 level of working of an Inverter
  • Ans. 

    An inverter has 5 levels of working: input, pre-driver, driver, output, and load.

    • Input stage receives the input signal and converts it to a digital signal.

    • Pre-driver stage amplifies the digital signal and sends it to the driver stage.

    • Driver stage amplifies the signal further and sends it to the output stage.

    • Output stage converts the amplified signal back to analog form.

    • Load stage receives the analog signal and drives t

  • Answered by AI
  • Q6. What is strong 1 and strong 0 concepts in an inverter
  • Ans. 

    Strong 1 and strong 0 are the maximum voltage levels that an inverter can output for logic 1 and logic 0 respectively.

    • Strong 1 is the maximum voltage level that an inverter can output for logic 1.

    • Strong 0 is the maximum voltage level that an inverter can output for logic 0.

    • These concepts are important in determining the noise margin of a digital circuit.

    • The noise margin is the difference between the minimum voltage lev...

  • Answered by AI
  • Q7. What you know about layout designing, which tool you have worked with
  • Ans. 

    Layout designing involves creating a physical representation of a circuit using CAD tools.

    • Layout designing is a crucial step in the physical design process of integrated circuits.

    • It involves placing and routing the components of a circuit to meet design specifications.

    • CAD tools commonly used for layout designing include Cadence Virtuoso, Synopsys IC Compiler, and Mentor Graphics Calibre.

    • Layout designers must consider f...

  • Answered by AI
  • Q8. Can you introduce yourself
  • Ans. 

    I am a Physical Design Engineer with experience in designing and optimizing integrated circuits.

    • I have a Bachelor's degree in Electrical Engineering

    • I have worked on projects involving ASIC design and verification

    • I am proficient in using tools such as Cadence and Synopsys

    • I have experience in optimizing power, area, and timing constraints

    • I am familiar with industry-standard design methodologies such as RTL-to-GDSII flow

  • Answered by AI
  • Q9. Which is your favorite subject throughout your course of study
  • Ans. 

    My favorite subject throughout my course of study is Digital Design.

    • I enjoyed learning about logic gates and how they can be used to create complex circuits.

    • I found the process of designing and testing digital circuits to be very satisfying.

    • I also appreciated the practical applications of digital design in fields like computer architecture and embedded systems.

    • I excelled in courses like Digital Logic Design and Compute...

  • Answered by AI
  • Q10. What is virtual ground concept in an op-amp
  • Ans. 

    Virtual ground is a concept where the non-inverting input of an op-amp is grounded to create a reference point for the inverting input.

    • Virtual ground is created by connecting the non-inverting input of an op-amp to ground.

    • This creates a reference point for the inverting input, which can be used to amplify the difference between the two inputs.

    • Virtual ground is commonly used in amplifier circuits and filters.

    • Examples of...

  • Answered by AI
  • Q11. Can a draw a basic transistor amplifier and explain
  • Ans. 

    A transistor amplifier is a circuit that uses a transistor to amplify the input signal.

    • A transistor amplifier consists of a transistor, a power supply, and input and output signals.

    • The transistor acts as a switch, controlling the flow of current through the circuit.

    • The input signal is applied to the base of the transistor, and the output signal is taken from the collector.

    • The gain of the amplifier is determined by the ...

  • Answered by AI
  • Q12. Why we prefer voltage divider bias circuit over others.
  • Ans. 

    Voltage divider bias circuit is preferred due to its stability and low sensitivity to temperature variations.

    • Provides stable bias voltage

    • Low sensitivity to temperature variations

    • Simple and easy to implement

    • Suitable for low power applications

    • Reduces noise and distortion

    • Examples: BJT amplifier circuits, op-amp circuits

  • Answered by AI
  • Q13. What is load line, What is difference between dc load line to that of ac load line
  • Ans. 

    Load line is a graphical representation of the relationship between voltage and current in a circuit.

    • DC load line represents the steady-state behavior of a circuit while AC load line represents the dynamic behavior of a circuit.

    • DC load line is a straight line while AC load line is a curved line.

    • DC load line is used to determine the operating point of a circuit while AC load line is used to analyze the small-signal beha...

  • Answered by AI
  • Q14. What is Q point, how does voltage divider bias fix Q point
  • Ans. 

    Q point is the operating point of a transistor. Voltage divider bias fixes Q point by setting the base voltage to a desired level.

    • Q point is the DC bias point of a transistor.

    • It is the point where the transistor operates in the active region.

    • Voltage divider bias sets the base voltage to a desired level, which in turn sets the Q point.

    • This ensures that the transistor operates in the desired region and provides the requi...

  • Answered by AI
  • Q15. What you know about stabilization concept in an amplifier
  • Ans. 

    Stabilization concept in an amplifier refers to the techniques used to prevent oscillations and ensure stable operation.

    • Stabilization is achieved by adding feedback components to the amplifier circuit

    • The feedback components can include resistors, capacitors, and inductors

    • Negative feedback is commonly used to stabilize amplifiers

    • Positive feedback can cause instability and oscillations

    • Stabilization techniques vary depend...

  • Answered by AI
  • Q16. Can draw n basic RC circuit for low pass filter and explain
  • Ans. 

    Yes, I can draw n basic RC circuits for low pass filter and explain.

    • An RC circuit consists of a resistor and a capacitor in series or parallel

    • The cutoff frequency of the low pass filter is determined by the values of R and C

    • The output voltage decreases as the frequency of the input signal increases

    • Examples of basic RC circuits include RC low pass filter, RC high pass filter, and RC bandpass filter

  • Answered by AI
  • Q17. How will be the charging and discharging of Capacitor in this circuit.
  • Ans. 

    The charging and discharging of capacitor in the circuit depends on the voltage and resistance of the circuit.

    • The capacitor charges when the voltage across it increases and discharges when the voltage decreases.

    • The rate of charging and discharging depends on the resistance of the circuit.

    • The time constant of the circuit determines the rate of charging and discharging.

    • The formula for time constant is T = R*C, where T is

  • Answered by AI
  • Q18. Can you draw the waveform for charging and discharging current.
  • Ans. 

    Yes, I can draw the waveform for charging and discharging current.

    • The waveform for charging current is a rising slope from zero to the maximum current value, followed by a plateau at the maximum value until the battery is fully charged.

    • The waveform for discharging current is a falling slope from the maximum current value to zero, followed by a plateau at zero until the battery is fully discharged.

    • The charging and disch...

  • Answered by AI
  • Q19. What are the conditions for an RC circuit to work as an integrator/differentiator Can you derive it with this circuit
  • Ans. 

    RC circuit works as integrator/differentiator under certain conditions. Can be derived with circuit analysis.

    • For an RC circuit to work as an integrator, the time constant (RC) should be large enough compared to the input signal frequency.

    • For an RC circuit to work as a differentiator, the time constant (RC) should be small enough compared to the input signal frequency.

    • The output voltage of an RC integrator circuit is pr...

  • Answered by AI
  • Q20. What is the difference between small signal analysis to that for large signal anaysis
  • Ans. 

    Small signal analysis is linear and deals with small variations around an operating point, while large signal analysis is nonlinear and deals with large variations.

    • Small signal analysis assumes that the circuit is linear and that the input signal is small enough to not affect the operating point of the circuit.

    • Large signal analysis deals with nonlinear circuits and assumes that the input signal is large enough to affec...

  • Answered by AI
  • Q21. How good are in programming. Rate out of 10
  • Ans. 

    I rate myself 8 out of 10 in programming.

    • I have experience in programming languages such as C++, Python, and Verilog.

    • I have developed scripts to automate tasks and improve efficiency.

    • I am constantly learning and improving my programming skills.

    • I have successfully completed several programming projects.

    • I am comfortable working with complex algorithms and data structures.

  • Answered by AI
  • Q22. What are second order effects in CMOS. Can you explain each one?
  • Ans. 

    Second order effects in CMOS and their explanation

    • Second order effects are non-linear effects that occur in CMOS devices

    • Some examples include channel length modulation, body effect, and drain-induced barrier lowering

    • Channel length modulation is the change in effective channel length due to the variation in drain-source voltage

    • Body effect is the change in threshold voltage due to the variation in substrate voltage

    • Drain-...

  • Answered by AI
  • Q23. How does the current equation changes when second order effects taken in account
  • Ans. 

    The current equation becomes more complex and includes additional terms when second order effects are considered.

    • Second order effects refer to non-linearities in the system that affect the current equation.

    • These effects can include things like parasitic capacitance, inductance, and resistance.

    • When second order effects are taken into account, the current equation may include additional terms such as higher order derivat...

  • Answered by AI
  • Q24. What you know about CMOS latch-up. Explain with help of circuitry.
  • Ans. 

    CMOS latch-up is a phenomenon where a parasitic thyristor is formed in a CMOS circuit, causing it to malfunction.

    • CMOS latch-up occurs when a parasitic thyristor is formed between the power supply and ground in a CMOS circuit.

    • This can happen when the voltage at the input or output pins exceeds the power supply voltage.

    • To prevent latch-up, designers use guard rings, substrate contacts, and other techniques to prevent the...

  • Answered by AI
  • Q25. How can we avoid latch up in a CMOS circuit
  • Ans. 

    Latch up in CMOS circuits can be avoided by implementing proper layout techniques and using guard rings.

    • Implement proper layout techniques

    • Use guard rings

    • Avoid asymmetric layout

    • Minimize substrate resistance

    • Use low-resistance substrate material

    • Avoid high substrate doping levels

    • Use ESD protection devices

    • Avoid high voltage gradients

    • Use proper power supply sequencing

  • Answered by AI
  • Q26. Why CMOS is preferred over NMOS and PMOS.
  • Ans. 

    CMOS is preferred over NMOS and PMOS due to its low power consumption, high noise immunity, and compatibility with digital circuits.

    • CMOS consumes less power than NMOS and PMOS.

    • CMOS has higher noise immunity due to complementary nature of transistors.

    • CMOS is compatible with digital circuits due to its ability to switch between high and low states.

    • NMOS and PMOS have higher power consumption and are not complementary in n...

  • Answered by AI
  • Q27. Draw cross sectional view an NMOS and explain its electrons flow level working
  • Ans. 

    An NMOS cross-sectional view and electron flow level working explanation.

    • NMOS stands for n-channel metal-oxide-semiconductor.

    • It is a type of MOSFET (metal-oxide-semiconductor field-effect transistor).

    • NMOS has a source, drain, and gate terminal.

    • When a voltage is applied to the gate, it creates an electric field that attracts electrons from the source to the drain.

    • The flow of electrons from source to drain is controlled ...

  • Answered by AI
  • Q28. Characteristics curve for NMOS, PMOS and CMOS
  • Ans. 

    Characteristics curve for NMOS, PMOS and CMOS are graphs that show the relationship between current and voltage.

    • NMOS curve shows that current increases with voltage until it reaches saturation

    • PMOS curve shows that current decreases with voltage until it reaches saturation

    • CMOS curve is a combination of NMOS and PMOS curves

    • CMOS curve shows that current flows only when both NMOS and PMOS are on

    • The threshold voltage is the

  • Answered by AI
  • Q29. Introduce yourself
  • Ans. 

    I am a Physical Design Engineer with experience in designing and optimizing integrated circuits.

    • I have a Bachelor's degree in Electrical Engineering

    • I have worked on multiple projects involving ASIC design and optimization

    • I am proficient in using EDA tools such as Cadence and Synopsys

    • I have experience in floorplanning, placement, and routing of digital circuits

    • I am familiar with industry-standard design methodologies su

  • Answered by AI
  • Q30. Why Intel?
  • Ans. 

    Intel is a leading technology company with a strong focus on innovation and cutting-edge products.

    • Intel has a reputation for being at the forefront of technological advancements

    • Intel invests heavily in research and development to create innovative products

    • Intel has a diverse range of products and services, providing opportunities for growth and development

    • Intel has a strong company culture that values collaboration, di

  • Answered by AI
  • Q31. What was the work in your previous company. Why you want to switch the company?
  • Ans. 

    I worked as a Physical Design Engineer in my previous company. I am looking for new challenges and opportunities to grow.

    • I was responsible for designing and implementing physical layouts of integrated circuits.

    • I collaborated with cross-functional teams to ensure timely delivery of projects.

    • I optimized designs for power, performance, and area.

    • I want to switch companies to gain exposure to new technologies and work on mo...

  • Answered by AI
  • Q32. One question to check how I deal with stress situations
  • Q33. One question to check how I Manage an Event Inside Intel
  • Q34. What is your salary expectation?
  • Ans. 

    I am open to discussing a salary that is commensurate with my experience and the responsibilities of the role.

    • I am flexible and open to negotiation

    • I am looking for a fair and competitive salary based on industry standards

    • I am willing to consider other benefits such as healthcare, retirement plans, and vacation time

    • I am interested in opportunities for growth and advancement within the company

  • Answered by AI
  • Q35. Any questions that you have to ask us?
  • Ans. 

    Yes, what are the biggest challenges your physical design team is currently facing?

    • Ask about the team's current projects and timelines

    • Inquire about any upcoming technology changes or advancements

    • Ask about the team's approach to problem-solving and collaboration

  • Answered by AI

Interview Preparation Tips

Round: Technical Interview
Experience: Basically they try know your technical knowledge through first, In fact this round is the more or less like an Elimination round where in you have to reply with little more explanation or until he moves to next question which mostly will be related to your answer. So jump into trouble by trying to make your own answer rather try to switch on to a topic that you well
Tips: A good grasp of Basic electronics and VLSI questions will help a lot in this round. Never go for an interview without brushing up your knowledge. Be prepared with self intro for atleast 2/3min such a way that any question from it can be answered with immense confidence level.

Round: Technical Interview
Experience: This was the round which I was able to perform well. I feel that the interviewer wanted to know more about my technical skills and hence more questions. A good preparation was required to tackle this round, and in fact I did. The interviewer was quite happy when I was able to give answer more than expected. NPTEL videos helped me a lot to face this round.
Tips: Be thorough with RC, RLC, circuit, its charging/discharging. Concept in transistor biasing, its fixing and stabilization have to known. Be ready with your subject of interest, and should be able to answer if asked from any corner of it.

Round: Technical Interview
Experience: As you can see, this round was more in VLSI stuffs. Since I said that I am not interested in programming, he changed the discussion into relevant domain. This round was more or less to check I fit into other positions also like Design Automation/Verification etc
Tips: Dont give an answer 'yes' for an area you dont know or rather you are not interested into
-> Take your own time to answer the question. Interviewer not more concerned about how fast you can answer.
-> I would suggestion you to watch this NPTEL video to learn about CMOS latch up. It helped me:-----?v=QlwcPjHpnH0

Round: HR Interview
Experience: More than a HR interview, it was more like an Behavioral round. The interview was taken by Skip level Manager. For last question, I asked 'what will be my actual work here and where can I find myself 2/3 years down the line?.
All the interviews where 1:1.

Tips: ->Never give answer 'no' for the last question I mentioned here
-> All the answers in this should be abide by ethics and values.
-> Know about the company and your work before hand.

Skill Tips: -> Be prepared well
-> Keep in mind that the Interviewer wont a preplanned set of questions to ask you and hence its all about how and what you answer. In fact, the whole Interview is just what you decide
-> Try to get rid of questions that you dont. Its better to say 'I dont know' rather than beating around the bush'
-> Be free out of Tension, take your own to answer, there is no harm in that.

Skills: Basic Digital Logic, Digital Design, Digital And Analogue Parts Of VLSI, VLSI, Basic Electronics, Analog And Digital Knowledge, Analog Integrated Circuits, CMOS Circuits, Analog Circuits
College Name: Government Model Engineering College, Thrikkakara

Skills evaluated in this interview

Interview experience
3
Average
Difficulty level
Moderate
Process Duration
Less than 2 weeks
Result
No response

I applied via LinkedIn and was interviewed in Jul 2023. There were 2 interview rounds.

Round 1 - Technical 

(4 Questions)

  • Q1. Floorplan strategies to calculate maximum macro counts that can be used in a block, placement constraints, congestion issues.
  • Ans. 

    Floorplan strategies involve calculating maximum macro counts, considering placement constraints and addressing congestion issues.

    • Floorplan strategies involve determining the maximum number of macros that can be accommodated within a block.

    • Placement constraints refer to the rules and guidelines that dictate where macros can be placed within the block.

    • Congestion issues arise when there is limited space or resources avai...

  • Answered by AI
  • Q2. Multi cycle paths, timing violations in reg2reg path.
  • Q3. Routing issues, signal integrity, IR drop analysis.
  • Q4. Logical DRC's, causes and fixing strategies.
Round 2 - Technical 

(3 Questions)

  • Q1. Issues and fixes faced during previous projects.
  • Q2. Placement, CTS, CMOS concepts
  • Q3. LVS, Design for manufacturing.

Skills evaluated in this interview

Interview Questionnaire 

9 Questions

  • Q1. Questions related to the work done at my previous company
  • Q2. Find if a given directed graph is cyclic or not
  • Ans. 

    To check if a directed graph is cyclic or not

    • Use Depth First Search (DFS) algorithm to traverse the graph

    • Maintain a visited set to keep track of visited nodes

    • Maintain a recursion stack to keep track of nodes in the current DFS traversal

    • If a node is visited and is already in the recursion stack, then the graph is cyclic

    • If DFS traversal completes without finding a cycle, then the graph is acyclic

  • Answered by AI
  • Q3. You have a stream of bytes from which you can read one byte at a time. You only have enough space to store one byte. After processing those bytes, you have to return a random byte. Note: The probability of...
  • Ans. 

    Return a random byte from a stream of bytes with equal probability.

    • Create a variable to store the count of bytes read

    • Create a variable to store the current random byte

    • For each byte read, generate a random number between 0 and the count of bytes read

    • If the random number is 0, store the current byte as the random byte

    • Return the random byte

  • Answered by AI
  • Q4. Find if a given Binary Tree is BST or not
  • Ans. 

    Check if a binary tree is a binary search tree or not.

    • Traverse the tree in-order and check if the values are in ascending order.

    • For each node, check if its value is greater than the maximum value of its left subtree and less than the minimum value of its right subtree.

    • Use recursion to check if all nodes in the tree satisfy the above condition.

  • Answered by AI
  • Q5. Devise an algorithm to determine the Nth-to-Last element in a singly linked list of unknown length. If N = 0, then your algorithm must return the last element. You should parse the list only once
  • Ans. 

    Algorithm to find Nth-to-Last element in a singly linked list of unknown length

    • Traverse the list and maintain two pointers, one at the beginning and one at Nth node from beginning

    • Move both pointers simultaneously until the second pointer reaches the end of the list

    • The first pointer will be pointing to the Nth-to-Last element

    • If N=0, return the last element

    • Parse the list only once

  • Answered by AI
  • Q6. Given an array of integers, print all possible permutations. Also explain your approach
  • Ans. 

    Print all possible permutations of an array of integers

    • Use recursion to swap elements and generate permutations

    • Start with the first element and swap it with each subsequent element

    • Repeat the process for the remaining elements

    • Stop when all elements have been swapped with the first element

    • Print each permutation as it is generated

  • Answered by AI
  • Q7. Design a Stack DS that also prints in O(1) the minimum element you pushed in the stack
  • Ans. 

    Design a stack that prints the minimum element pushed in O(1)

    • Use two stacks, one for storing elements and another for storing minimums

    • When pushing an element, compare it with the top of minimum stack and push the smaller one

    • When popping an element, pop from both stacks

    • To get the minimum element, just return the top of minimum stack

  • Answered by AI
  • Q8. Given a linked list with loop, how would you find the starting point of the loop ?
  • Ans. 

    To find the starting point of a loop in a linked list, use Floyd's cycle-finding algorithm.

    • Use two pointers, one moving at twice the speed of the other.

    • When they meet, move one pointer to the head of the list and keep the other at the meeting point.

    • Move both pointers one step at a time until they meet again, which is the starting point of the loop.

  • Answered by AI
  • Q9. Find a number a matrix mat[m][n] where all the rows and columns are sorted non-decreasingly. What will be the complexity of the solution
  • Ans. 

    To find a number in a matrix where all rows and columns are sorted non-decreasingly. Complexity of the solution.

    • Use binary search to find the number in each row and column

    • Start from the top-right corner or bottom-left corner to optimize search

    • Time complexity: O(m log n) or O(n log m) depending on the starting corner

  • Answered by AI

Interview Preparation Tips

Skills: Algorithm, Data structure
College Name: Na

Skills evaluated in this interview

Interview Questionnaire 

3 Questions

  • Q1. Asked me about my answer for a question in the logical test and asked me to find mistake
  • Q2. Some tree question
  • Q3. Some array question

Interview Preparation Tips

Round: Test
Experience: Just logical questions. Maybe create a DFA and NFA.
Duration: 1 hour
Total Questions: 20

Round: Coding
Experience: Given two questions. Each question is written like a story, but once you get the idea, it will be a simple question

College Name: Govt. Model Engineering College

I applied via Campus Placement

Interview Questionnaire 

3 Questions

  • Q1. They asked me optimise the code I had written for the first question
  • Q2. Given a binary tree, find out the maximum sum path from root to leaf. This problem, but they said tree has only positive integers. -----/ . To store the path I had used global array. They asked me alternat...
  • Q3. Given a list of words. Given three operations find out the minimum steps to reach from source string to destination string. Basically, -----/ this is the problem with some modification. For this question I...
  • Ans. 

    The question is about finding the minimum steps to reach from a source string to a destination string using three operations.

    • BFS and DFS are graph traversal techniques that can be used to solve this problem.

    • BFS is typically used when finding the shortest path or exploring all possible paths in a graph.

    • DFS is useful when searching for a specific path or exploring deeply into a graph.

    • In this case, BFS can be used to find...

  • Answered by AI

Interview Preparation Tips

Round: Test
Experience: • 1 question was on time complexity of searching an unsorted array.
• 2 questions were on recursion, ie, number of recursive calls.
• 1 question on analysing given function on string.
• 1 question was on probability(Two hotels, say A and B. Probability of moving from A to B is 2/3, staying at A is 1/3. Probability of moving from B to A and staying at B is 1/2. If they make decisions each hour, and if they were at A at 7:00 pm, what is the probability that they will be at B at 10:00 pm).
• If a set has elements {1,2,3,4 .... n}. Then what is the sum of elements of it's power set. (Ex: S = {1,2}. Then power set is {{},{1},{2},{1,2}}. The sum is 6.
• If a set has elements {1,2,3,4,5,6,7,8,9,10}. Then how many subsets of 3 elements has no consecutive elements.
• 1 question was on designing a DFA for a string starting with a and ending with c and has at least b in it.
• 1 question had machine instructions. We had to find out minimum number of cycles needed to execute the given set of instructions. (a) If the instructions are executed in the given order. (b) If the instructions are executed in random order.
• 1 puzzle on bridges.

Tips: In this round they not only see the answer. They also verify how you approached(So, give correct explanation to your answers).
Duration: 90 minutes
Total Questions: 10

Round: Coding Round
Experience: Two questions were there. 3 hours duration.

1. Long question, I don't remember fully. I'll just give input/output examples. It was basically on string decoding. If jon2snow3 is there the decoded string will be jonjonsnowjonjonsnowjonjonsnow. Given a string and an integer k we have print the kth character in the decoded string
input:
jon2snow3
8
output:
n

2. Given an array and an integer k return the number of contiguous sub arrays whose sum is divisible by k.
input format:
n k

input:
4 5
10 0 4 5

output:
4

explaination: {10},{0},{10,0},{5} are the sub arrays with sum divisible by 5.


Tips: You will have lots of time, so try to optimise the solution if you can. Remember here also they review each individual's code.

Round: Technical Interview
Experience: They will help you a lot if you are stuck at some point in the question. You have to be smart enough to grasp the clue.
Tips: They only ask questions only on data structures and algorithms.

Skill Tips: You have to be strong in coding. Algorithm questions will be mostly on dynamic programming. Data structures questions are mostly on trees.
Skills: C Programming, Maths(esp Probability), Algorithms And Data Structures
Duration: 5
College Name: JSS Mahavidyapeetha Sri Jayachamarajendra College Of Engineering, Mysore

Skills evaluated in this interview

Software Engineer Interview Questions & Answers

Intel user image Niranjhana Narayanan

posted on 4 Dec 2016

I applied via Campus Placement and was interviewed in Dec 2016. There were 5 interview rounds.

Interview Questionnaire 

2 Questions

  • Q1. Why UDP and not TCP in project
  • Ans. 

    UDP is preferred over TCP in this project due to its low latency and lightweight nature.

    • UDP is a connectionless protocol, which means it does not establish a direct connection between the sender and receiver.

    • UDP is faster than TCP as it does not have the overhead of establishing and maintaining a connection.

    • UDP is suitable for applications where real-time data transmission is crucial, such as video streaming or online ...

  • Answered by AI
  • Q2. How would you clear the 7th bit in a 32 bit register
  • Ans. 

    To clear the 7th bit in a 32-bit register, perform a bitwise AND operation with a mask that has all bits set to 1 except the 7th bit.

    • Create a mask with the 7th bit set to 0 and all other bits set to 1

    • Perform a bitwise AND operation between the register and the mask

    • Store the result back in the register

  • Answered by AI

Interview Preparation Tips

Round: Test
Experience: Questions were based on C concepts, given piece of code, find error, output, etc then data structures, bit manipulation, a few aptitude questions were also there (around 5-7).
Tips: Practice aptitude, C, data structures (geeksforgeeks.org is a good source).
Duration: 1 hour
Total Questions: 30

Round: Technical + HR Interview
Experience: I was asked to explain project in detail, I had done projects on embedded, so was asked about that, details like what fields did you use in that structure, why this implementation and not some related other. Memory management, network communications, operating systems. Then questions on C concepts like memory allocation, function pointers, then data structures like linked lists, then bit manipulation in registers. Questions from electrical coursework. Then later, why higher studies, would you still go for higher studies if you had a good job at a company, why etc.
Tips: Be thorough with C (know your Kernighan & Ritchie) and be prepared to go into details about your projects.

Skills: C, Data Structures, Coursework Understanding, Project And Internship
College Name: IIT Madras

Skills evaluated in this interview

Interview Preparation Tips

Round: Test
Experience: The selection procedure is a test followed by tech interview and an HR interview.
The test had two parts:
 Aptitude (common across all profiles)
 A tech. test (separate for each profile)

Round: Interview
Experience: The tech interview was the important one and the HR interview was just about knowing the student and vice-versa. The tech interview was more concentrated on the basics and more importance was given to the approach of solving the problem rather than solving the problem itself.
No CGPA cutoff.

Round: Interview
Experience: Not very important.

General Tips: The work is well structured and executed. There is a lot of opportunity for more technical learning. Interns are also included into the teams and this helps the intern on knowing about the things going around them and gets an overall view of how things work.
As a whole, the work is very good, and exceeds all the expectations of the students.
College Name: IIT Madras

Interview Questionnaire 

9 Questions

  • Q1. Tree questions related like traversal?
  • Q2. Locate the sum of 2 numbers in a linear array (Unsorted and sorted) and their complexities
  • Ans. 

    Locate sum of 2 numbers in a linear array (unsorted and sorted) and their complexities

    • For unsorted array, use nested loops to compare each element with every other element until the sum is found

    • For sorted array, use two pointers approach starting from the beginning and end of the array and move them towards each other until the sum is found

    • Complexity for unsorted array is O(n^2) and for sorted array is O(n)

  • Answered by AI
  • Q3. Pointers with increment/decrement, address of and value at operators (++,–,*,&)
  • Ans. 

    Pointers are used to manipulate memory addresses and values in C++. Increment/decrement, address of and value at operators are commonly used.

    • Incrementing a pointer moves it to the next memory location of the same data type

    • Decrementing a pointer moves it to the previous memory location of the same data type

    • The address of operator (&) returns the memory address of a variable

    • The value at operator (*) returns the value sto

  • Answered by AI
  • Q4. A point and a rectangle is present with the given coordinates. How will you determine whether the point is inside or outside the rectangle?
  • Ans. 

    To determine if a point is inside or outside a rectangle, we check if the point's coordinates fall within the rectangle's boundaries.

    • Check if the point's x-coordinate is greater than the left edge of the rectangle

    • Check if the point's x-coordinate is less than the right edge of the rectangle

    • Check if the point's y-coordinate is greater than the top edge of the rectangle

    • Check if the point's y-coordinate is less than the b...

  • Answered by AI
  • Q5. There is a point inside the rectangle. How will you determine the line that passes through the point and divides the rectangle into 2 equal halves?
  • Ans. 

    To find line that divides rectangle into 2 equal halves through a point inside it.

    • Find the center of the rectangle

    • Draw a line from the center to the given point

    • Extend the line to the opposite side of the rectangle

    • The extended line will divide the rectangle into 2 equal halves

  • Answered by AI
  • Q6. There is a scheme which contains 8-bit and 16-bit signed numbers. How many such combinations are possible?
  • Ans. 

    There are multiple combinations of 8-bit and 16-bit signed numbers. How many such combinations are possible?

    • There are 2^8 (256) possible combinations of 8-bit signed numbers.

    • There are 2^16 (65,536) possible combinations of 16-bit signed numbers.

    • To find the total number of combinations, we can add the number of combinations of 8-bit and 16-bit signed numbers.

    • Therefore, the total number of possible combinations is 256 +

  • Answered by AI
  • Q7. You are given an array of elements. Some/all of them are duplicates. Find them in 0(n) time and 0(1) space. Property of inputs – Number are in the range of 1..n where n is the limit of the array
  • Ans. 

    Find duplicates in an array of elements in 0(n) time and 0(1) space.

    • Use the property of inputs to your advantage

    • Iterate through the array and mark elements as negative

    • If an element is already negative, it is a duplicate

    • Return all the negative elements as duplicates

  • Answered by AI
  • Q8. Given a array of digits. print all combination of of these i.e all no formed by these. repetition allowed. and then repetition not allowed example: i/p: arr={1,2,3} o/p: (without repetition) 123, 132, 213,...
  • Q9. Questions on project

Interview Preparation Tips

Round: Test
Duration: 90 minutes
Total Questions: 3

Round: HR Interview
Experience: HR interview was all about my projects, my background and a few more typical HR questions. It was pretty easy to answer them.

Skills: Algorithm, Data structure, C++
College Name: IIT ROORKEE

Skills evaluated in this interview

I applied via Referral and was interviewed before Sep 2020. There was 1 interview round.

Interview Questionnaire 

2 Questions

  • Q1. Basic c programming
  • Q2. Previous experience questions

Interview Preparation Tips

Interview preparation tips for other job seekers - Be honest. And prepare well in data structures
Contribute & help others!
anonymous
You can choose to be anonymous

Synopsys Interview FAQs

How many rounds are there in Synopsys RTL Design and Verification Engineer interview?
Synopsys interview process usually has 2 rounds. The most common rounds in the Synopsys interview process are Aptitude Test and Technical.
What are the top questions asked in Synopsys RTL Design and Verification Engineer interview?

Some of the top questions asked at the Synopsys RTL Design and Verification Engineer interview -

  1. Difference between task and funct...read more
  2. Questions about veri...read more

Recently Viewed

INTERVIEWS

10405090xyzabc

No Interviews

INTERVIEWS

Polestar Solutions & Services India

No Interviews

JOBS

Polestar Solutions & Services India

No Jobs

INTERVIEWS

Jaguar Land Rover

No Interviews

INTERVIEWS

Collins Aerospace

No Interviews

SALARIES

Polestar Solutions & Services India

INTERVIEWS

Alvarez & Marsal

No Interviews

SALARIES

Collins Aerospace

SALARIES

Polestar Solutions & Services India

INTERVIEWS

Indian Army

No Interviews

Tell us how to improve this page.

Synopsys RTL Design and Verification Engineer Interview Process

based on 1 interview

Interview experience

3
  
Average
View more

Interview Questions from Similar Companies

Intel Interview Questions
4.2
 • 215 Interviews
Texas Instruments Interview Questions
4.1
 • 120 Interviews
Molex Interview Questions
3.9
 • 53 Interviews
Lam Research Interview Questions
3.7
 • 44 Interviews
View all
R&D Engineer
148 salaries
unlock blur

₹0 L/yr - ₹0 L/yr

Senior R&D Engineer
100 salaries
unlock blur

₹0 L/yr - ₹0 L/yr

Staff Engineer
89 salaries
unlock blur

₹0 L/yr - ₹0 L/yr

Security Consultant
60 salaries
unlock blur

₹0 L/yr - ₹0 L/yr

Applications Engineer
58 salaries
unlock blur

₹0 L/yr - ₹0 L/yr

Explore more salaries
Compare Synopsys with

Cadence Design Systems

4.1
Compare

Mentor Graphics

4.0
Compare

Ansys Software Private Limited

3.9
Compare

Infineon Technologies

3.9
Compare
Did you find this page helpful?
Yes No
write
Share an Interview
Rate your experience using AmbitionBox
Terrible
Terrible
Poor
Poor
Average
Average
Good
Good
Excellent
Excellent