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I applied via LinkedIn and was interviewed in May 2022. There were 2 interview rounds.
SoC architecture consists of multiple components like CPU, memory, peripherals, and interconnects. Transactions are done through buses.
SoC architecture includes a CPU, memory, peripherals, and interconnects
Interconnects are used to connect the components and enable communication
Transactions are done through buses like AXI, AHB, or APB
The components can be customized based on the application requirements
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posted on 29 Aug 2024
UVM (Universal Verification Methodology) basic principle is to provide a standardized methodology for verifying digital designs.
UVM is based on SystemVerilog and provides a framework for creating reusable verification environments
It promotes the use of object-oriented programming techniques for creating modular and scalable testbenches
UVM encourages the use of constrained-random stimulus generation and coverage-driven ...
posted on 29 Feb 2024
I applied via Campus Placement and was interviewed in Jan 2024. There was 1 interview round.
posted on 5 Apr 2024
posted on 15 Apr 2024
I applied via Referral and was interviewed before Apr 2023. There were 3 interview rounds.
I applied via Referral and was interviewed in Aug 2021. There was 1 interview round.
posted on 29 Nov 2024
Toggle the bits of given input
Create a mask with all bits set to 1
XOR the input with the mask to toggle the bits
Repeat the process for each bit position
Print a star pattern using loops
Use nested loops to print the desired pattern
Increment the number of stars in each row to create the pattern
Example: for a pattern with 5 rows - * , ** , *** , **** , *****
posted on 2 Oct 2024
I applied via campus placement at Netaji Subhas Institute of Technology (NSIT) and was interviewed in Sep 2024. There were 2 interview rounds.
Basic aptitude-10 question,digital moderate -Question,analog moderate -10 question,verilog and system verilog -10 question
posted on 15 Jan 2025
A FIFO checker is a verification component used to monitor and validate the behavior of a First-In-First-Out buffer in a design.
Implement a monitor that tracks the input and output operations of the FIFO buffer
Check that the data is read out in the same order it was written in
Verify that the FIFO buffer does not overflow or underflow
Use assertions to flag any violations of FIFO behavior
Example: Monitor the write and re...
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