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Marquee Semiconductor Verification Engineer Interview Questions and Answers

Updated 22 Mar 2024

Marquee Semiconductor Verification Engineer Interview Experiences

1 interview found

Interview experience
4
Good
Difficulty level
Moderate
Process Duration
Less than 2 weeks
Result
Selected Selected

I applied via Campus Placement and was interviewed before Mar 2023. There was 1 interview round.

Round 1 - Technical 

(4 Questions)

  • Q1. Digital design logic questions.
  • Q2. Please explain how bubble sort works and write thr logic for it..
  • Ans. 

    Bubble sort is a simple sorting algorithm that repeatedly steps through the list, compares adjacent elements, and swaps them if they are in the wrong order.

    • Compare adjacent elements and swap if necessary

    • Repeat until no more swaps are needed

    • Time complexity is O(n^2)

    • Example: [5, 3, 8, 2, 1] -> [3, 5, 2, 1, 8] -> [3, 2, 1, 5, 8] -> [2, 1, 3, 5, 8] -> [1, 2, 3, 5, 8]

  • Answered by AI
  • Q3. What is setup and hold time? How does it impact digital design?
  • Ans. 

    Setup and hold time are timing constraints in digital design that ensure data is stable before and after the clock edge.

    • Setup time is the amount of time data must be stable before the clock edge for it to be reliably captured.

    • Hold time is the amount of time data must be stable after the clock edge for it to be reliably captured.

    • Violating setup time can lead to metastability issues, while violating hold time can result ...

  • Answered by AI
  • Q4. How to create a 2 select line MUX out of NAND gates only?
  • Ans. 

    A 2 select line MUX can be created using NAND gates by cascading multiple gates in a specific configuration.

    • Use two NAND gates to create an AND gate by connecting the inputs of the NAND gates together and taking the output from both gates.

    • Use another NAND gate to create an OR gate by connecting the outputs of the two AND gates to the inputs of the OR gate.

    • Connect the select lines to the inputs of the AND gates and the ...

  • Answered by AI

Interview Preparation Tips

Topics to prepare for Marquee Semiconductor Verification Engineer interview:
  • Analog basics
  • Digital design basics
  • KMap
  • Verilog

Skills evaluated in this interview

Marquee Semiconductor Interview FAQs

How many rounds are there in Marquee Semiconductor Verification Engineer interview?
Marquee Semiconductor interview process usually has 1 rounds. The most common rounds in the Marquee Semiconductor interview process are Technical.
What are the top questions asked in Marquee Semiconductor Verification Engineer interview?

Some of the top questions asked at the Marquee Semiconductor Verification Engineer interview -

  1. How to create a 2 select line MUX out of NAND gates on...read more
  2. What is setup and hold time? How does it impact digital desi...read more
  3. Please explain how bubble sort works and write thr logic for i...read more

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