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I applied via Referral and was interviewed in Aug 2021. There was 1 interview round.
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posted on 29 Aug 2024
UVM (Universal Verification Methodology) basic principle is to provide a standardized methodology for verifying digital designs.
UVM is based on SystemVerilog and provides a framework for creating reusable verification environments
It promotes the use of object-oriented programming techniques for creating modular and scalable testbenches
UVM encourages the use of constrained-random stimulus generation and coverage-driven ...
posted on 29 Feb 2024
I applied via Campus Placement and was interviewed in Jan 2024. There was 1 interview round.
posted on 5 Apr 2024
posted on 15 Apr 2024
I applied via Referral and was interviewed before Apr 2023. There were 3 interview rounds.
I applied via Company Website and was interviewed in Jan 2023. There were 2 interview rounds.
posted on 10 Feb 2024
I applied via Campus Placement and was interviewed in Jan 2024. There were 2 interview rounds.
Mcq questions based on aptitude(a bit ) and digital design, VLSI, Clock related questions
I applied via Referral and was interviewed before Jun 2023. There were 2 interview rounds.
FIFO full condition occurs when the FIFO buffer is completely filled with data.
Occurs when the number of items in the FIFO buffer reaches its maximum capacity
Further writes to the FIFO buffer are blocked until some data is read out
Can lead to data loss if not managed properly
posted on 22 Sep 2022
General ECE questions and all are MCQ. Basic electronics also important
based on 2 reviews
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