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Synopsys Physical Design Engineer Interview Questions and Answers

Updated 21 Sep 2024

Synopsys Physical Design Engineer Interview Experiences

3 interviews found

Interview experience
4
Good
Difficulty level
Moderate
Process Duration
Less than 2 weeks
Result
Not Selected

I applied via Campus Placement and was interviewed in Aug 2024. There were 3 interview rounds.

Round 1 - Aptitude Test 

Aotitude,core que on all subjects in ece

Round 2 - Technical 

(2 Questions)

  • Q1. INTERNSHIP EXPERIENCE
  • Ans. 

    I completed a 6-month internship at XYZ Company where I gained hands-on experience in physical design tools and methodologies.

    • Worked on floorplanning, placement, and routing of digital designs

    • Utilized tools such as Cadence Innovus and Synopsys ICC

    • Collaborated with cross-functional teams to optimize design performance

  • Answered by AI
  • Q2. ON DSD,VLSI,ANALOG ELECTRONICS
Round 3 - HR 

(2 Questions)

  • Q1. APTITUDE,MATH,VLSI,DSD
  • Q2. VLSI (HARD QUESTION BASED ON INDUSTRY LEVEL LIKE ON CIRCUIT HE GIVES ONE SCENARIO U HAVE TO ANSWER IT)

Interview Preparation Tips

Interview preparation tips for other job seekers - LEARN BASICS WELL
Interview experience
4
Good
Difficulty level
-
Process Duration
-
Result
-
Round 1 - Technical 

(1 Question)

  • Q1. Sdc basics TCL coding

Physical Design Engineer Interview Questions Asked at Other Companies

asked in Intel
Q1. What are the conditions for an RC circuit to work as an integrato ... read more
asked in Intel
Q2. What are second order effects in CMOS. Can you explain each one?
asked in Intel
Q3. Can a draw a basic transistor amplifier and explain
asked in Intel
Q4. What is strong 1 and strong 0 concepts in an inverter
Q5. What is an ICG? How would you use it in the design?
Interview experience
4
Good
Difficulty level
-
Process Duration
-
Result
-
Round 1 - Technical 

(1 Question)

  • Q1. Congestion analysis

Interview questions from similar companies

Interview experience
3
Average
Difficulty level
Moderate
Process Duration
Less than 2 weeks
Result
No response

I applied via LinkedIn and was interviewed in Jul 2023. There were 2 interview rounds.

Round 1 - Technical 

(4 Questions)

  • Q1. Floorplan strategies to calculate maximum macro counts that can be used in a block, placement constraints, congestion issues.
  • Ans. 

    Floorplan strategies involve calculating maximum macro counts, considering placement constraints and addressing congestion issues.

    • Floorplan strategies involve determining the maximum number of macros that can be accommodated within a block.

    • Placement constraints refer to the rules and guidelines that dictate where macros can be placed within the block.

    • Congestion issues arise when there is limited space or resources avai...

  • Answered by AI
  • Q2. Multi cycle paths, timing violations in reg2reg path.
  • Q3. Routing issues, signal integrity, IR drop analysis.
  • Q4. Logical DRC's, causes and fixing strategies.
Round 2 - Technical 

(3 Questions)

  • Q1. Issues and fixes faced during previous projects.
  • Q2. Placement, CTS, CMOS concepts
  • Q3. LVS, Design for manufacturing.

Skills evaluated in this interview

Interview experience
3
Average
Difficulty level
-
Process Duration
-
Result
-
Round 1 - Technical 

(2 Questions)

  • Q1. Toggle the bits of given input
  • Ans. 

    Toggle the bits of given input

    • Create a mask with all bits set to 1

    • XOR the input with the mask to toggle the bits

    • Repeat the process for each bit position

  • Answered by AI
  • Q2. Clear the set bit
Round 2 - Technical 

(2 Questions)

  • Q1. Print the star pattern
  • Ans. 

    Print a star pattern using loops

    • Use nested loops to print the desired pattern

    • Increment the number of stars in each row to create the pattern

    • Example: for a pattern with 5 rows - * , ** , *** , **** , *****

  • Answered by AI
  • Q2. Microprocessor microcontroller topics are asked

Skills evaluated in this interview

Interview experience
5
Excellent
Difficulty level
-
Process Duration
-
Result
-
Round 1 - One-on-one 

(2 Questions)

  • Q1. Assertions and coverage
  • Q2. Umv basic principle
  • Ans. 

    UVM (Universal Verification Methodology) basic principle is to provide a standardized methodology for verifying digital designs.

    • UVM is based on SystemVerilog and provides a framework for creating reusable verification environments

    • It promotes the use of object-oriented programming techniques for creating modular and scalable testbenches

    • UVM encourages the use of constrained-random stimulus generation and coverage-driven ...

  • Answered by AI

Interview Preparation Tips

Interview preparation tips for other job seekers - Prepare basics
Interview experience
4
Good
Difficulty level
-
Process Duration
-
Result
-
Round 1 - Technical 

(1 Question)

  • Q1. They asked from Digital, COA
Round 2 - Technical 

(1 Question)

  • Q1. They asked the concepts of COA
Round 3 - HR 

(1 Question)

  • Q1. First started with Puzzle and then about company
Interview experience
5
Excellent
Difficulty level
Moderate
Process Duration
-
Result
-

I applied via Referral and was interviewed in Apr 2024. There was 1 interview round.

Round 1 - Technical 

(2 Questions)

  • Q1. Simple FSM given similar to mux and asked for testcases and assertions.
  • Q2. Coverage to write transitions of states.
  • Ans. 

    Coverage-driven verification techniques are used to ensure all possible state transitions are exercised.

    • Coverage metrics like state, transition, and toggle coverage can be used to track the completeness of state transitions.

    • Writing directed tests to cover specific state transitions can help achieve higher coverage.

    • Random stimulus generation can also be used to explore different state transitions.

    • Functional coverage can...

  • Answered by AI
Interview experience
3
Average
Difficulty level
Moderate
Process Duration
2-4 weeks
Result
Not Selected

I applied via Campus Placement and was interviewed in Jan 2024. There was 1 interview round.

Round 1 - Technical 

(2 Questions)

  • Q1. Basics of analog , digital and vlsi
  • Q2. On face to face interview, they asked me abt my projects , digital, little analog , vlsi ( verilog), microcontrollers and c programming

Interview Preparation Tips

Interview preparation tips for other job seekers - Prepare well on your basics
Interview experience
4
Good
Difficulty level
Moderate
Process Duration
Less than 2 weeks
Result
Not Selected

I applied via LinkedIn and was interviewed in Oct 2023. There were 2 interview rounds.

Round 1 - Aptitude Test 

40 aptitude qns and some mcqs on basic programming

Round 2 - Technical 

(4 Questions)

  • Q1. I was asked to write two sum, palindrome function and merge sort code in whatever language I'm comfortable in
  • Q2. Two sum- return true or false
  • Ans. 

    Given an array of integers, determine if there are two numbers that add up to a specific target.

    • Iterate through the array and store each element in a hash set.

    • For each element, check if the difference between the target and the element exists in the hash set.

    • If the difference exists, return true; otherwise, continue iterating.

    • Example: nums = [2, 7, 11, 15], target = 9. The function should return true as 2 + 7 = 9.

  • Answered by AI
  • Q3. Merge sort function code
  • Q4. Palindromic string or not

Skills evaluated in this interview

Synopsys Interview FAQs

How many rounds are there in Synopsys Physical Design Engineer interview?
Synopsys interview process usually has 1-2 rounds. The most common rounds in the Synopsys interview process are Technical, Aptitude Test and HR.
How to prepare for Synopsys Physical Design Engineer interview?
Go through your CV in detail and study all the technologies mentioned in your CV. Prepare at least two technologies or languages in depth if you are appearing for a technical interview at Synopsys. The most common topics and skills that interviewers at Synopsys expect are Physical Design, PNR, STA, ASIC and CAD.
What are the top questions asked in Synopsys Physical Design Engineer interview?

Some of the top questions asked at the Synopsys Physical Design Engineer interview -

  1. VLSI (HARD QUESTION BASED ON INDUSTRY LEVEL LIKE ON CIRCUIT HE GIVES ONE SCENAR...read more
  2. ON DSD,VLSI,ANALOG ELECTRON...read more
  3. APTITUDE,MATH,VLSI,...read more

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Synopsys Physical Design Engineer Interview Process

based on 4 interviews

Interview experience

3.8
  
Good
View more

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Synopsys Physical Design Engineer Salary
based on 21 salaries
₹9 L/yr - ₹23 L/yr
79% more than the average Physical Design Engineer Salary in India
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4.0/5

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