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I applied via LinkedIn and was interviewed before Apr 2022. There were 2 interview rounds.
1 NAND gate can be used to make 2 combinations of inverter.
A NAND gate can be used to make an inverter by connecting both inputs together.
The output of the NAND gate will be the inverted input.
Thus, there are 2 possible combinations of inverter using just 1 NAND gate.
Using 2:1 mux, implement inverter, AND gate, OR gate.
For inverter, connect one input to select line and other input to ground
For AND gate, connect one input to select line and other input to input signal, output is inverted
For OR gate, connect one input to select line and other input to input signal, output is not inverted
Use truth tables to verify functionality
A 4:1 mux can be implemented using two 2:1 muxes.
Connect the select line of both 2:1 muxes to the same select line of the 4:1 mux.
Connect the output of one 2:1 mux to the input of the other 2:1 mux.
Connect the inputs of both 2:1 muxes to the corresponding inputs of the 4:1 mux.
The output of the 4:1 mux is the output of the second 2:1 mux.
Ring, Johnson, Sync and Async counters are types of digital counters used in electronics.
Ring counter is a circular shift register with only one flip-flop set to 1 at a time.
Johnson counter is a modified ring counter with complemented output of the last flip-flop fed back to the input.
Sync counters use a common clock signal for all flip-flops while Async counters use individual clock signals.
Examples of Sync counters a...
Shift registers are sequential circuits that can store and shift data bits.
Shift registers are made up of flip-flops that store data bits.
Data can be shifted left or right through the register.
Shift registers can be used for serial-to-parallel or parallel-to-serial conversion.
Examples of shift registers include the Serial-in-Parallel-out (SIPO) and Parallel-in-Serial-out (PISO) registers.
Flip-flop conversion from DFF to JKFF
Determine the excitation table for JK flip-flop
Use the excitation table to derive the input equations for J and K
Replace D input with J and K inputs in DFF circuit
Verify the functionality of the converted JKFF circuit
Verilog supports various data types including integer, real, reg, wire, and time.
Integer data type is used for whole numbers
Real data type is used for decimal numbers
Reg data type is used for sequential logic
Wire data type is used for combinational logic
Time data type is used for simulation time
Data types can be declared using keywords like 'integer', 'real', 'reg', 'wire', and 'time'
Data types can also be declared wit...
Tasks are concurrent and functions are sequential in execution.
Tasks can run concurrently and can communicate with each other using shared variables.
Functions are executed sequentially and return a value to the calling function.
Tasks can be used for parallel processing and can be scheduled by the operating system.
Functions are used for modular programming and can be called from other functions or tasks.
Example: A task ...
Blocking waits for a process to complete before moving to the next, while non-blocking allows for concurrent execution.
Blocking assignments use '=' operator, while non-blocking use '<=' operator.
Blocking assignments are executed sequentially, while non-blocking assignments are executed concurrently.
Blocking assignments are used for combinational logic, while non-blocking assignments are used for sequential logic.
Exampl
Universal gates are logic gates that can be used to implement any Boolean function.
Universal gates are NAND and NOR gates.
They are called universal because they can be used to implement any Boolean function.
This is because NAND and NOR gates are functionally complete.
This means that any Boolean function can be expressed using only NAND or NOR gates.
Other gates like AND, OR, and NOT gates are not functionally complete.
F...
I applied via Campus Placement and was interviewed before Apr 2023. There were 2 interview rounds.
1. FSM Coding
2. Counter
3. Flip-flops (D and JK)
4. Final year project-related questions
I applied via LinkedIn and was interviewed before Jun 2022. There were 3 interview rounds.
I applied via Campus Placement and was interviewed in Mar 2022. There were 2 interview rounds.
Time and work
profit and losses
numerics
Explaining latch and flip-flop differences and advantages of clock in VLSI engineering.
Latches are level-sensitive while flip-flops are edge-sensitive
Latches are faster but consume more power than flip-flops
Flip-flops are more reliable and less prone to glitches than latches
Clocks are used to synchronize the operation of digital circuits
Advantages of clock include reducing power consumption, improving timing accuracy,
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Get interview-ready with Top Cerium Systems Interview Questions
I applied via Campus Placement and was interviewed before Jun 2023. There were 3 interview rounds.
Gud we have to go through the basics
Digital electronics verilog
I applied via LinkedIn and was interviewed before Feb 2023. There were 2 interview rounds.
I applied via Campus Placement and was interviewed before Mar 2023. There were 2 interview rounds.
Medium difficulty level aptitude
Written test
Aptitude & digital
A 32:1 mux can be implemented using 2:1 mux by cascading them in multiple stages.
Divide the 32 inputs into groups of 2 and use 2:1 mux to select one of the inputs from each group.
Cascading 16 such 2:1 muxes will give 16 outputs.
Again divide the 16 outputs into groups of 2 and use 2:1 mux to select one of the outputs from each group.
Cascading 2 such 2:1 muxes will give the final output.
I applied via Campus Placement and was interviewed in Aug 2021. There were 3 interview rounds.
Digital, analog, aptitude
The question is about CMOS, MUX, and Verilog coding.
CMOS stands for Complementary Metal-Oxide-Semiconductor and is a type of technology used in integrated circuits.
A MUX (multiplexer) is a device that selects one of several input signals and forwards the selected input into a single output line.
Verilog is a hardware description language used to model digital circuits and systems.
Verilog code for a 2:1 MUX: module mux(o...
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