Perceptive Analytics Interview Questions and Answers

Implement 2 stage XOR gate using 2 stage NAND gate.

• Construct 2 stage NAND gate using 4 NAND gates.

• Connect the output of first stage NAND gate to the input of second stage NAND gate.

• Connect the output of second stage NAND gate to the input of first stage NAND gate.

• The output of second stage NAND gate is the output of the XOR gate.

Implementing dff using 2:1 mux

• Connect the input to the select line of the mux

• Connect the output of the mux to one of the inputs of the mux

• Connect the output of the dff to the other input of the mux

• Connect the output of the mux to the input of the dff

Grey code is a binary numeral system where two successive values differ in only one bit.

• To convert Grey code to binary, start with the most significant bit and XOR each bit with the previous bit.

• For example, to convert Grey code 1010 to binary: 1 XOR 0 = 1, 0 XOR 1 = 1, 1 XOR 1 = 0, 0 XOR 1 = 1. So, the binary equivalent is 1101.

The Boolean expression of a circuit represents its logic functionality using logical operators.

• Identify the logic gates used in the circuit (AND, OR, NOT, etc.)

• Create a truth table to determine the output for all possible input combinations

• Write the Boolean expression based on the truth table and logic gates used

Latch is level sensitive while flip flop is edge sensitive. Flip flop has clock input while latch does not.

• Latch is level sensitive, meaning it changes output based on the input level, while flip flop is edge sensitive, changing output on clock edge

• Flip flop has clock input to control when the output changes, while latch does not have a clock input

• Flip flop is more commonly used in sequential circuits for storing data, while latch is used in level triggered circuits

Physical design flow involves converting a logical design into a physical layout.

• The process starts with floorplanning and power planning

• Placement and routing are done to create a physical layout

• Timing analysis and optimization are performed to meet timing constraints

• Design rule check (DRC) and layout versus schematic (LVS) checks are done to ensure correctness

• Finally, the layout is verified through signoff checks before tapeout