Mirafra Technologies RTL Design and Verification Engineer Interview Questions and Answers

Q1. Write a FIFO checker
Add your answer

Q1. The question was draw cmos inverter transfer characteristics and by varying some parameters they asked their effects on it.
Add your answer

Q1. Regarding verification uvm
Add your answer
Q2. About projects and clients
Add your answer

Digital,Verilog, SV based questions with some quants.

SV & UVM concepts with some examples would be fine.

Q1. Self Introduction
Add your answer
Q2. Why do you want to join this organisation.
Ans. 
I want to join this organization because of its reputation for innovation and commitment to excellence in design and verification engineering.
• I am impressed by the company's track record of developing cutting-edge technologies.

• I believe that working at this organization will provide me with opportunities for professional growth and development.

• I am excited about the chance to collaborate with a team of talented enginee...read more
Answered by AI
Add your answer

Q1. What is the functional coverage ?
Ans. 
Functional coverage is a metric used to measure how much of the design functionality has been exercised by the verification environment.
• Functional coverage is used to ensure that all the features of the design have been tested.

• It is a measure of how much of the design functionality has been exercised by the verification environment.

• Functional coverage is typically defined in terms of coverage points, which are specific...read more
Answered by AI
Add your answer
Q2. What is randomisation
Ans. 
Randomisation is a technique used in verification to generate random test cases.
• Randomisation is used to increase the probability of finding bugs in a design.

• It involves generating random inputs to test the functionality of a design.

• Randomisation can be used in both simulation and formal verification.

• It helps in identifying corner cases and edge cases that may not be covered by directed tests.

• Randomisation can be contr...read more
Answered by AI
Add your answer

Q1. Asked the working experience and the related skills to the new job
Add your answer

Q1. Coding questions in Verilog, Systemverilog, random constraints such as how to write a onehot in different ways
Add your answer

Q1. Asked the expectation of the base salary and overall compensation
Add your answer

Q1. Related to verification
Add your answer
Q2. Related to verification
Add your answer

Q1. Related to verification
Add your answer