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I applied via Company Website and was interviewed before Dec 2023. There were 3 interview rounds.
Digital,Verilog, SV based questions with some quants.
SV & UVM concepts with some examples would be fine.
I want to join this organization because of its reputation for innovation and commitment to excellence in design and verification engineering.
I am impressed by the company's track record of developing cutting-edge technologies.
I believe that working at this organization will provide me with opportunities for professional growth and development.
I am excited about the chance to collaborate with a team of talented enginee...
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posted on 2 Oct 2024
I applied via campus placement at Netaji Subhas Institute of Technology (NSIT) and was interviewed in Sep 2024. There were 2 interview rounds.
Basic aptitude-10 question,digital moderate -Question,analog moderate -10 question,verilog and system verilog -10 question
posted on 24 Jul 2024
randc behavior generates random complex numbers with specified distribution
Use randc to generate random complex numbers
Specify distribution using arguments like mean, variance, etc.
Example: randc(10, 1, 2) generates 10 random complex numbers with mean 1 and variance 2
posted on 29 Apr 2024
I applied via campus placement at Indian Institute of Technology (IIT), Kharagpur and was interviewed before Apr 2023. There were 2 interview rounds.
I plan to continue advancing my skills in design verification engineering and eventually move into a leadership role.
Continue taking relevant courses and certifications to stay updated on industry trends
Seek opportunities to lead projects and teams to gain leadership experience
Network with professionals in the field to learn from their experiences and insights
posted on 20 Jun 2022
I applied via LinkedIn and was interviewed before Jun 2021. There were 4 interview rounds.
Medium level
RTL design, test bench , Simulation.
posted on 29 Nov 2024
Toggle the bits of given input
Create a mask with all bits set to 1
XOR the input with the mask to toggle the bits
Repeat the process for each bit position
Print a star pattern using loops
Use nested loops to print the desired pattern
Increment the number of stars in each row to create the pattern
Example: for a pattern with 5 rows - * , ** , *** , **** , *****
posted on 12 Aug 2024
I applied via campus placement at Birla Institute of Technology and Science (BITS), Pilani and was interviewed in Jul 2024. There was 1 interview round.
To predict if a 32 bit number is divisible by 8, design a circuit using gates.
Use a circuit with AND, OR, and NOT gates to check if the last three bits of the number are all zeros.
If the last three bits are zeros, then the number is divisible by 8.
For example, if the 32 bit number is 11010000, the last three bits are zeros, so it is divisible by 8.
posted on 29 Feb 2024
I applied via Campus Placement and was interviewed in Jan 2024. There was 1 interview round.
I applied via Referral and was interviewed before Jan 2022. There were 3 interview rounds.
Mostly on TB components coding, different scenario coding..
Mostly on past project experience, different implementation on those projects.
Seeking new challenges and growth opportunities in the field of verification engineering.
Desire to work on more complex projects
Opportunity to learn and apply new technologies
Seeking a more collaborative and supportive work environment
Career advancement and professional development
Company restructuring or downsizing
Relocation or commute concerns
posted on 27 Sep 2022
I applied via Company Website and was interviewed in Mar 2022. There were 3 interview rounds.
Had basic aptitude questions, verilog , c programming, digital electronics, analog electronics,computer architecture.
Senior Engineer
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