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I applied via LinkedIn and was interviewed before Jun 2021. There were 4 interview rounds.
Medium level
RTL design, test bench , Simulation.
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posted on 2 Oct 2024
I applied via campus placement at Netaji Subhas Institute of Technology (NSIT) and was interviewed in Sep 2024. There were 2 interview rounds.
Basic aptitude-10 question,digital moderate -Question,analog moderate -10 question,verilog and system verilog -10 question
posted on 7 May 2024
I applied via Referral and was interviewed in Apr 2024. There was 1 interview round.
Coverage-driven verification techniques are used to ensure all possible state transitions are exercised.
Coverage metrics like state, transition, and toggle coverage can be used to track the completeness of state transitions.
Writing directed tests to cover specific state transitions can help achieve higher coverage.
Random stimulus generation can also be used to explore different state transitions.
Functional coverage can...
posted on 23 Nov 2022
Verilog, c++ pointers, mosfets
UART protocol can be used to transmit and receive data between two devices.
UART can be used to communicate between a microcontroller and a computer
UART can be used to send and receive data between two microcontrollers
UART can be used to interface with sensors and actuators
UART can be used to implement a simple command/response protocol
UART can be used to implement a data logging system
UART can be used to receive signals from a microcontroller.
Connect the UART pins of the microcontroller to the UART pins of the receiving device.
Configure the UART settings such as baud rate, parity, and stop bits.
Use a UART library or write code to read the incoming data from the UART buffer.
Process the received data as required by the application.
posted on 29 Apr 2024
I applied via campus placement at Indian Institute of Technology (IIT), Kharagpur and was interviewed before Apr 2023. There were 2 interview rounds.
I plan to continue advancing my skills in design verification engineering and eventually move into a leadership role.
Continue taking relevant courses and certifications to stay updated on industry trends
Seek opportunities to lead projects and teams to gain leadership experience
Network with professionals in the field to learn from their experiences and insights
posted on 29 Nov 2024
Toggle the bits of given input
Create a mask with all bits set to 1
XOR the input with the mask to toggle the bits
Repeat the process for each bit position
Print a star pattern using loops
Use nested loops to print the desired pattern
Increment the number of stars in each row to create the pattern
Example: for a pattern with 5 rows - * , ** , *** , **** , *****
posted on 12 Aug 2024
I applied via campus placement at Birla Institute of Technology and Science (BITS), Pilani and was interviewed in Jul 2024. There was 1 interview round.
To predict if a 32 bit number is divisible by 8, design a circuit using gates.
Use a circuit with AND, OR, and NOT gates to check if the last three bits of the number are all zeros.
If the last three bits are zeros, then the number is divisible by 8.
For example, if the 32 bit number is 11010000, the last three bits are zeros, so it is divisible by 8.
posted on 29 Feb 2024
I applied via Campus Placement and was interviewed in Jan 2024. There was 1 interview round.
I applied via Approached by Company and was interviewed before Aug 2021. There was 1 interview round.
Design muxes and write code for Fibonacci series
Design a 2:1 mux using Verilog or VHDL
Implement the Fibonacci series using a for loop or recursion
Connect the output of the mux to select between the two Fibonacci numbers
Test the design with different inputs and verify the output
posted on 27 Sep 2022
I applied via Company Website and was interviewed in Mar 2022. There were 3 interview rounds.
Had basic aptitude questions, verilog , c programming, digital electronics, analog electronics,computer architecture.
Analog Design Engineer
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