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Mirafra Technologies Design & Verification Engineer Interview Questions and Answers

Updated 28 Jul 2024

Mirafra Technologies Design & Verification Engineer Interview Experiences

3 interviews found

Interview experience
3
Average
Difficulty level
-
Process Duration
-
Result
-
Round 1 - Technical 

(5 Questions)

  • Q1. Write code randc behaviour
  • Ans. 

    randc behavior generates random complex numbers with specified distribution

    • Use randc to generate random complex numbers

    • Specify distribution using arguments like mean, variance, etc.

    • Example: randc(10, 1, 2) generates 10 random complex numbers with mean 1 and variance 2

  • Answered by AI
  • Q2. Functinal coverage
  • Q3. Code coverage related questions
  • Q4. Monitor and scoreboard connections
  • Q5. Project related questions

Skills evaluated in this interview

Interview experience
5
Excellent
Difficulty level
-
Process Duration
-
Result
-
Round 1 - One-on-one 

(2 Questions)

  • Q1. Project questions
  • Q2. Sv and uvm basics
Round 2 - One-on-one 

(2 Questions)

  • Q1. Pcie basic questions
  • Q2. SV and UVM basics

Design & Verification Engineer Interview Questions Asked at Other Companies

asked in Frenus Tech
Q1. 1. XOR gate 2. How you compare two 4 bit numbers only using gates ... read more
Q2. Why $cast is used? Types of arrays
Q3. Explain setup time and hold time and what is the importance of se ... read more
Q4. What is mux? What are the use of select lines in mux?
asked in Samsung
Q5. how to call an interface signal at sequence level in uvm?

I applied via LinkedIn and was interviewed in May 2022. There were 4 interview rounds.

Round 1 - Resume Shortlist 
Pro Tip by AmbitionBox:
Keep your resume crisp and to the point. A recruiter looks at your resume for an average of 6 seconds, make sure to leave the best impression.
View all tips
Round 2 - Aptitude Test 

This round consists of technical test which was focusing on electronics subjects.

Round 3 - Technical 

(1 Question)

  • Q1. In this round , questions were asked in digital design , verilog and projects.
Round 4 - HR 

(1 Question)

  • Q1. In this round as usual HR questions were asked.

Interview Preparation Tips

Interview preparation tips for other job seekers - Waste company Mirafra Technologies, they said that we will send offer letters to you within 2 or 3 days then they will not send offer letters and let you keep waiting for months.
In HR interview threy will say you " Best of Luck for future endeavors with Mirafra " but they will not send you offer letters. Hahahahahahha
It is not good for freshers, they are playing with freshers

Design & Verification Engineer Jobs at Mirafra Technologies

View all

Interview questions from similar companies

Interview experience
4
Good
Difficulty level
Moderate
Process Duration
2-4 weeks
Result
Selected Selected

I applied via Campus Placement and was interviewed before Jun 2023. There were 2 interview rounds.

Round 1 - Technical 

(1 Question)

  • Q1. Digital logics , Verilog , System verilog , UVM , logical riddle
Round 2 - Technical 

(1 Question)

  • Q1. Projects related questions
Interview experience
5
Excellent
Difficulty level
-
Process Duration
-
Result
-

I applied via Job Portal

Round 1 - One-on-one 

(1 Question)

  • Q1. 1) Explain flipflops 2) UVM Architecture 3)constraints
  • Ans. 

    Flip-flops are sequential logic circuits used to store and manipulate binary data.

    • Flip-flops are basic building blocks of digital circuits.

    • They can store a single bit of information, either 0 or 1.

    • Flip-flops have two stable states: set and reset.

    • They are used to store and transfer data in sequential circuits.

    • Examples of flip-flops include D flip-flop, JK flip-flop, and T flip-flop.

  • Answered by AI
Interview experience
4
Good
Difficulty level
Moderate
Process Duration
2-4 weeks
Result
Selected Selected

I applied via Walk-in and was interviewed before Jul 2023. There were 2 interview rounds.

Round 1 - Aptitude Test 

All aptitude topics covered

Round 2 - Technical 

(2 Questions)

  • Q1. And gate code in behavioral
  • Ans. 

    Implementing an AND gate in behavioral code

    • Use if statements to check if both inputs are high

    • Assign the output to high if both inputs are high

    • Use Verilog or VHDL syntax depending on the language being used

  • Answered by AI
  • Q2. Difference between Ff & latch
  • Ans. 

    FF is edge-triggered, stores data on clock edge. Latch is level-sensitive, stores data as long as enable signal is active.

    • FF stores data on clock edge, latch stores data as long as enable signal is active

    • FF has two stable states (0 or 1), latch has one stable state (depends on enable signal)

    • FF is used for sequential circuits, latch is used for level-sensitive circuits

    • Example: D flip-flop (FF) vs SR latch

  • Answered by AI

Interview Preparation Tips

Topics to prepare for Wipro Design & Verification Engineer interview:
  • Design
Interview preparation tips for other job seekers - all basics covered

I applied via Walk-in and was interviewed before Dec 2020. There were 3 interview rounds.

Interview Questionnaire 

3 Questions

  • Q1. Basic Programming questions.
  • Q2. Fibonacci program
  • Q3. OOPS concepts.

Interview Preparation Tips

Interview preparation tips for other job seekers - Prepare basic OOPS concepts and basic programs.

I applied via Campus Placement and was interviewed before Feb 2020. There were 6 interview rounds.

Interview Questionnaire 

4 Questions

  • Q1. Was interviewed as fresher?
  • Q2. Written test conducted? with verbal ability test ? GD
  • Q3. How would u deal with a problematic situation when you are working in a team?
  • Q4. What are your plans about higher studies?

Interview Preparation Tips

Interview preparation tips for other job seekers - it was basic with apptiude test and attitiude test.

Interview Questionnaire 

3 Questions

  • Q1. What is your role in current project
  • Q2. Why should we hire you
  • Q3. What the major challenges you have faced in your earlier project ?

Interview Questionnaire 

2 Questions

  • Q1. What is your key roles and responsiblity in the organization.
  • Q2. How to deploy ivr application in servers.
  • Ans. 

    IVR application can be deployed in servers using various deployment methods.

    • Choose a deployment method based on the application requirements and server environment.

    • Common deployment methods include manual deployment, automated deployment, and containerization.

    • Ensure that all necessary dependencies and configurations are included in the deployment package.

    • Test the application thoroughly after deployment to ensure it is

  • Answered by AI

Interview Preparation Tips

Interview preparation tips for other job seekers - Be confident specify your key skills answered the questions accurately.

Skills evaluated in this interview

Mirafra Technologies Interview FAQs

How many rounds are there in Mirafra Technologies Design & Verification Engineer interview?
Mirafra Technologies interview process usually has 2-3 rounds. The most common rounds in the Mirafra Technologies interview process are Technical, One-on-one Round and Aptitude Test.
How to prepare for Mirafra Technologies Design & Verification Engineer interview?
Go through your CV in detail and study all the technologies mentioned in your CV. Prepare at least two technologies or languages in depth if you are appearing for a technical interview at Mirafra Technologies. The most common topics and skills that interviewers at Mirafra Technologies expect are UVM, Design Verification, System Verilog, SOC Verification and ASIC Verification.
What are the top questions asked in Mirafra Technologies Design & Verification Engineer interview?

Some of the top questions asked at the Mirafra Technologies Design & Verification Engineer interview -

  1. write code randc behavi...read more
  2. In this round , questions were asked in digital design , verilog and projec...read more
  3. Monitor and scoreboard connecti...read more

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Mirafra Technologies Design & Verification Engineer Interview Process

based on 2 interviews

Interview experience

4
  
Good
View more
Mirafra Technologies Design & Verification Engineer Salary
based on 26 salaries
₹6 L/yr - ₹14.3 L/yr
35% more than the average Design & Verification Engineer Salary in India
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