AmbitionBox
Interview Questions
- Reviews
- Salaries
- Interview Questions
- About Company
- Benefits
- Jobs
- Office Photos
- Community
Add office photos
i
DIGICOMM Semiconductor
Compare
Filter interviews by
DIGICOMM Semiconductor Interview Questions, Process, and Tips
Top DIGICOMM Semiconductor Interview Questions and Answers
- Q1. What is the setup and hold time and different techniques to fix the setup and hold time violations?asked in Physical Design Engineer interview
- Q2. What are the different techniques to minimize congestion?asked in Physical Design Engineer interview
- Q3. What is useful skew, negative skew and positive skew?asked in Physical Design Engineer interview
DIGICOMM Semiconductor Interview Experiences
6 interviews found
I applied via Approached by Company and was interviewed in Apr 2023. There were 2 interview rounds.
(8 Questions)
- Q1. What are the PD inputs and outputs
- Ans.
PD inputs are design specifications and constraints, while outputs are physical layout of the design.
Inputs include design specifications, constraints, technology libraries, and floorplan.
Outputs include physical layout, placement of components, routing of wires, and design verification.
Example: Input - RTL design, clock frequency, power constraints. Output - GDSII layout, timing analysis report.
- Q2. Describe each stage of PNR flow
- Ans.
PNR flow consists of synthesis, floorplanning, placement, clock tree synthesis, routing, and signoff stages.
Synthesis: Convert RTL code to gate-level netlist
Floorplanning: Define chip area, core, and I/O locations
Placement: Place gates in specific locations to meet timing constraints
Clock tree synthesis: Create clock distribution network
Routing: Connect gates with wires while considering timing and congestion
Signoff: V...
- Q3. What are the different techniques to minimize congestion?
- Ans.
Techniques to minimize congestion include buffer insertion, wire spreading, and layer assignment.
Buffer insertion: Adding buffers to critical paths to improve timing and reduce congestion.
Wire spreading: Distributing wires evenly to reduce congestion in specific areas.
Layer assignment: Properly assigning different signal layers to reduce congestion on a single layer.
- Q4. What is the setup and hold time and different techniques to fix the setup and hold time violations?
- Ans.
Setup and hold time are timing constraints in digital circuits. Techniques to fix violations include adjusting clock skew, buffering signals, and optimizing routing.
Setup time is the minimum amount of time a data input must be stable before the clock edge for proper operation.
Hold time is the minimum amount of time a data input must be stable after the clock edge for proper operation.
Techniques to fix setup and hold ti...
- Q5. What is signal integrity?
- Ans.
Signal integrity refers to the quality of an electrical signal as it travels through a circuit or system.
It involves ensuring that the signal remains clear and undistorted from the transmitter to the receiver.
Factors affecting signal integrity include impedance matching, noise, crosstalk, and reflections.
Signal integrity analysis is crucial in high-speed digital design to prevent data errors and ensure reliable communi...
- Q6. What is crosstalk and noise and how to fix it?
- Ans.
Crosstalk is unwanted interference between signals on adjacent lines, while noise is random unwanted signals that can degrade performance.
Crosstalk occurs when signals on adjacent lines interfere with each other due to coupling effects.
Noise is random unwanted signals that can be caused by various sources such as electromagnetic interference or power supply fluctuations.
To fix crosstalk, techniques like spacing out lin...
- Q7. What is clock latency, skew and jitter?
- Ans.
Clock latency is the delay between the clock signal being generated and reaching the destination, skew is the variation in arrival times of the clock signal at different destinations, and jitter is the variation in the period of the clock signal.
Clock latency is the delay between the clock signal being generated and reaching the destination.
Skew is the variation in arrival times of the clock signal at different destina...
- Q8. What is useful skew, negative skew and positive skew?
- Ans.
Useful skew, negative skew, and positive skew are terms used in physical design to describe timing constraints.
Useful skew refers to intentional delay added to certain paths to meet timing requirements.
Negative skew occurs when data arrives later than expected, leading to potential timing violations.
Positive skew occurs when data arrives earlier than expected, potentially causing setup time violations.
Skew can be adjus...
Interview Preparation Tips
- STATIC TIMING ANALYSIS
- Physical Design
- FORMAL VERIFICATION
- Physical Verification
Skills evaluated in this interview
Top DIGICOMM Semiconductor Physical Design Engineer Interview Questions and Answers
Physical Design Engineer Interview Questions asked at other Companies
Selected
(2 Questions)
- Q1. Regarding verification uvm
- Q2. About projects and clients
Interview Preparation Tips
Verification Engineer Interview Questions asked at other Companies
(1 Question)
- Q1. Vlsi , physics design analog layout
(1 Question)
- Q1. Physical design
Software Engineer Interview Questions asked at other Companies
I applied via Campus Placement and was interviewed in Apr 2022. There were 2 interview rounds.
(1 Question)
- Q1. Question was all about digital and electronic devices
Interview Preparation Tips
Electronic devices
Digital electronics
These all subjects will help you
Graduate Engineer Trainee (Get) Interview Questions asked at other Companies
DIGICOMM Semiconductor interview questions for popular designations
I applied via LinkedIn and was interviewed in Feb 2022. There were 2 interview rounds.
(1 Question)
- Q1. 1. What is CMOS? 2. What is latch? 3. What is the difference between latch and flip flops? 4. How to make a metastable system stable? 5. V-I characteristics of MOSFET? 6. What is pinch-off? 7. What is dyna...
- Ans.
A technical interview for Engineer Trainee covering topics such as CMOS, latch, flip flops, MOSFET, and dynamic memory.
CMOS stands for Complementary Metal-Oxide-Semiconductor and is a type of technology used in microprocessors and digital logic circuits.
A latch is a type of digital circuit that can store one bit of information.
The main difference between a latch and a flip flop is that a flip flop has a clock input and...
Interview Preparation Tips
- Digital Electronics
- Analog circuit
- Semiconductor physics
Engineer Trainee Interview Questions asked at other Companies
I applied via Naukri.com and was interviewed in Sep 2021. There were 3 interview rounds.
Interview Questionnaire
2 Questions
- Q1. How to decide floor plan is good Or bad in the design
- Ans.
A good floor plan should optimize area, minimize congestion, and ensure signal integrity.
Optimize area utilization
Minimize congestion and routing complexity
Ensure signal integrity and minimize noise
Consider power and thermal constraints
Ensure ease of design changes and modifications
- Q2. What are the checks your do in offer post floor plan
- Ans.
Checks after floor plan in physical design engineering
Timing analysis to ensure timing constraints are met
Power analysis to ensure power constraints are met
Signal integrity analysis to ensure signal quality
Design rule check to ensure adherence to design rules
Physical verification to ensure layout is correct
Noise analysis to ensure noise constraints are met
Interview Preparation Tips
Top DIGICOMM Semiconductor Physical Design Engineer Interview Questions and Answers
Physical Design Engineer Interview Questions asked at other Companies
Jobs at DIGICOMM Semiconductor
Top trending discussions
Interview questions from similar companies
Furness Engineer & Shift Incharge (Supervisor) Interview Questions & Answers
TDK India Private Limited
Anonymous
posted on 21 Feb 2025
Selected
I was interviewed in Jan 2025.
(4 Questions)
- Q1. What do you know about transformers and the types of losses associated with them?
- Ans.
Transformers are electrical devices that transfer electrical energy between two or more circuits through electromagnetic induction.
Transformers are used to increase or decrease voltage levels in electrical circuits.
There are two main types of losses associated with transformers: copper losses and iron losses.
Copper losses occur due to the resistance of the copper windings in the transformer and are proportional to the ...
- Q2. What are the details regarding power loss, core losses, hysteresis loss, and eddy current loss?
- Ans.
Power loss in electrical systems can be categorized into core losses, hysteresis loss, and eddy current loss.
Core losses occur in the magnetic core of transformers and include hysteresis and eddy current losses.
Hysteresis loss is caused by the reversal of magnetization in the core material, leading to energy dissipation in the form of heat.
Eddy current loss is caused by circulating currents induced in the core material...
- Q3. What are the types of strategies for reducing losses in the current transformation process?
- Ans.
Strategies for reducing losses in the transformation process include implementing lean manufacturing principles, improving maintenance practices, and investing in employee training.
Implementing lean manufacturing principles to eliminate waste and improve efficiency
Improving maintenance practices to prevent breakdowns and reduce downtime
Investing in employee training to enhance skills and knowledge
Utilizing technology t
- Q4. What are the applications of high frequency in transformers, and how does it affect power generation and transformation?
- Ans.
High frequency in transformers is used in applications such as power distribution, induction heating, and medical equipment.
High frequency transformers are used in power distribution systems to step up or step down voltage levels efficiently.
They are also used in induction heating applications for processes like welding, melting, and heat treatment.
In medical equipment, high frequency transformers are used in devices l...
(3 Questions)
- Q1. Can you describe your previous companies and the job roles you held there, as well as the related skills you learned from those experiences?
- Ans.
I have worked in two companies in the past, where I held roles as a Furness Engineer and Shift Incharge. I gained skills in maintenance, supervision, and problem-solving.
Worked as a Furness Engineer at Company A, responsible for maintaining and troubleshooting furnaces
Promoted to Shift Incharge at Company B, overseeing production shifts and managing a team of technicians
Learned skills in maintenance, supervision, probl...
- Q2. What do you know about transducers, switching circuits, RTD, and SCADA PLC automation based on your previous job experiences?
- Ans.
I have extensive knowledge and experience with transducers, switching circuits, RTD, and SCADA PLC automation from my previous job roles.
Transducers are devices that convert one form of energy into another, such as a pressure transducer converting pressure into an electrical signal.
Switching circuits are used to control the flow of current in electronic devices, such as relays or MOSFETs.
RTD stands for Resistance Tempe...
- Q3. Details about ISO certification required for a company. EHS, OH&S, QMS - details about it, CAPA, RCA, FMEA, why why analysis, PDCA details about it?
(2 Questions)
- Q1. What is your family background, including their occupations? Are you open to working rotational shifts as well as night shifts?
- Ans.
My family background is diverse, with members in various occupations. I am open to working rotational and night shifts.
My family background is diverse, with members in occupations such as teachers, engineers, and business owners.
I am open to working rotational shifts as it allows for a variety in work schedule and night shifts if required for the job.
I understand the importance of flexibility in work hours and am willi
- Q2. What do you know about this company and the background of the job? What are your expectations regarding salary and benefits?
- Ans.
The company is a leading engineering firm with a focus on providing high-quality services. The job involves overseeing engineering operations and managing shifts.
Company is known for its expertise in engineering services
Job involves supervising engineering operations and shift management
Expectations for salary and benefits should be competitive with industry standards
(1 Question)
- Q1. What is the notice period required for your previous job, when would you be able to join us, and do you require any cab or pick-and-drop service?
- Ans.
Notice period is 30 days, can join after that, no cab or pick-and-drop service required.
Notice period for previous job is 30 days
Can join after completing notice period
No requirement for cab or pick-and-drop service
Interview Preparation Tips
VLSI Design and Verification Engineer Interview Questions & Answers
MediaTek India Technology
Anonymous
posted on 14 Oct 2024
I applied via Referral and was interviewed in Sep 2024. There were 2 interview rounds.
(5 Questions)
- Q1. For the first round t is only only.
- Q2. UVM-Phases,config db,resource db,asked me to write code for my projects mentioned in resume
- Q3. AMBA protocols(mentioned in resume) pslave error,decode error,signals,arbitration,interleaving.
- Q4. UVM architecture,verification flow
- Q5. First round mostly focussed on my communication skills and projects mentioned in my resume.For my friend they showed a PPT of questions just followed them.
(4 Questions)
- Q1. It is a face to face interview,Only focussed on technical questions.They have a common ppt with technical questions .They will show those questions ask you to write answers on a paper.
- Q2. 1.waveform shown asked to find the expression-XOR gate. 2.parity checker and parity generator truthtable and verilog code. 3.modports,clocking blocks and interface sv code. for (addr=something,data=somethi...
- Q3. Verilog FIFO code Assertion waveform shown sv code for it APB protocol waveforms Protocols signals if you mention them protocol address calculations coverage code types of array and their syntax
- Q4. For technical round they focus on coding only,don't forget to see all sv topics coding structure.
Software Engineer Interview Questions & Answers
Mirafra Technologies
Anonymous
posted on 31 Oct 2024
I applied via Walk-in and was interviewed in Oct 2024. There were 3 interview rounds.
(5 Questions)
- Q1. OOPS concept and All Major pillars with Scanrio-based questions asked on Abstract class and Interface
- Q2. .Net MVC and .Net Core based on program.cs file and Dependency Injection and Middleware in deep
- Q3. Pattern question and check string Palindrome
- Q4. SQL Queries around 4th highest salary of Employee
- Q5. All basic programming concept checking like having prefix and postfix expression problem solving on paper
(4 Questions)
- Q1. TechnoManagerial Round Collection question to find about number of character present in the word Mirafra with live coding F2F
- Q2. API testing ang REST API Concept
- Q3. Professional Journey
- Q4. Project Details
(2 Questions)
- Q1. It was a director round but say you need to give again technical round ,they wasted my time and money.
- Q2. SQL Queries on pen and paper
Interview Preparation Tips
I applied via Naukri.com and was interviewed in Sep 2024. There were 3 interview rounds.
(6 Questions)
- Q1. Merge intervals ( Leetcode)
- Q2. Buy and sell stocks II (Leetcode)
- Q3. Runtime polymorphism and how it works vptr and vtable
- Ans.
Runtime polymorphism in C++ is achieved through virtual functions, vptr (virtual pointer), and vtable (virtual table).
Runtime polymorphism allows objects of different classes to be treated as objects of a common superclass.
Virtual functions are declared in a base class and overridden in derived classes to achieve polymorphism.
vptr is a pointer that points to the vtable of an object, allowing dynamic binding of virtual ...
- Q4. Which version of c++ you use
- Ans.
I primarily use C++17, but I am familiar with earlier versions as well.
I am comfortable working with features introduced in C++17 such as structured bindings and constexpr if
I have experience with earlier versions like C++11 and C++14
I stay updated with the latest features and improvements in C++ standards
- Q5. Design patterns
- Q6. Have you used any windows api's?
- Ans.
Yes, I have used Windows API's extensively in my previous projects.
I have used Windows API's for tasks such as creating windows, handling messages, and interacting with system resources.
Examples include using functions like CreateWindow, SendMessage, and ReadFile.
I have also worked with specific Windows API's like Winsock for networking and WinINet for internet-related tasks.
(2 Questions)
- Q1. One debugging question was given which will test knowledge on copy constructor, copy assignment, their return type move constructor, move assignment shallow copy, deep copy runtime polymorphism pointer ini...
- Q2. What is dynamic_cast where it can fail and what will happen in that case
- Ans.
dynamic_cast is a C++ operator used for safe downcasting of pointers and references in polymorphic classes.
dynamic_cast is used to safely downcast a pointer or reference from a base class to a derived class.
It can fail if the object being casted is not of the target type, in which case it returns a null pointer for pointers or throws a std::bad_cast exception for references.
Dynamic_cast can only be used with pointers o...
(5 Questions)
- Q1. Same debugging question while making it advance how will you handle in case there is data member of pointer to int array in deep copy how will you ensure that it does delete previous data in case new opera...
- Q2. What is union in c++
- Ans.
Union in C++ is a data structure that allows storing different data types in the same memory location.
Unions are similar to structures but all members share the same memory location.
Only one member of a union can be accessed at a time.
Unions are useful when you need to store different data types in the same memory space.
Example: union MyUnion { int i; float f; };
Example: MyUnion u; u.i = 10; // Accessing integer member
- Q3. What is weak pointer
- Ans.
Weak pointer is a type of smart pointer in C++ that does not control the lifetime of the object it points to.
Weak pointers are used to break circular references in shared pointers.
They do not increase the reference count of the object.
They are used in scenarios where the object may be deleted while there are still weak pointers pointing to it.
- Q4. What are processes and threads memory is allocated to what process or threads? what is mutex and semaphore how many threads/process can you launch at a time what is meaning of core in 4-core system what is...
- Ans.
Processes and threads are units of execution in a computer system. Memory is allocated to processes. Mutex and semaphore are synchronization mechanisms. Core refers to a processing unit in a multi-core system. Context switching is the process of switching between different processes or threads.
Processes are independent units of execution with their own memory space and resources.
Threads are lightweight units of executi...
- Q5. What is this pointer tell me situation where only this pointer can be used nothing else will work
Skills evaluated in this interview
DIGICOMM Semiconductor Interview FAQs
Some of the top questions asked at the DIGICOMM Semiconductor interview -
Tell us how to improve this page.
DIGICOMM Semiconductor Interviews By Designations
- DIGICOMM Semiconductor Physical Design Engineer Interview Questions
- DIGICOMM Semiconductor Engineer Trainee Interview Questions
- DIGICOMM Semiconductor Graduate Engineer Trainee (Get) Interview Questions
- DIGICOMM Semiconductor Software Engineer Interview Questions
- DIGICOMM Semiconductor Verification Engineer Interview Questions
Interview Questions for Popular Designations
DIGICOMM Semiconductor Interview Process
based on 3 interviews
Interview experience
Interview Questions from Similar Companies
DIGICOMM Semiconductor Reviews and Ratings
based on 51 reviews
Rating in categories
Hyderabad / Secunderabad,
Bangalore / Bengaluru
5-15 Yrs
Not Disclosed
|
Physical Design Engineer
42
salaries
|  ₹3 L/yr - ₹12.3 L/yr |
|
Analog Layout Engineer
13
salaries
| ₹1.8 L/yr - ₹8 L/yr |
|
Senior Engineer
7
salaries
| ₹8.5 L/yr - ₹23 L/yr |
|
HR Executive
7
salaries
| ₹2.8 L/yr - ₹4 L/yr |
|
Senior Physical Design Engineer
7
salaries
| ₹8 L/yr - ₹18 L/yr |
Intel
Analog Devices
Broadcom
Micron Technology
- Home >
- Interviews >
- DIGICOMM Semiconductor Interview Questions
