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DIGICOMM Semiconductor Physical Design Engineer Interview Questions, Process, and Tips
Top DIGICOMM Semiconductor Physical Design Engineer Interview Questions and Answers
- Q1. What is the setup and hold time and different techniques to fix the setup and hold time violations?
- Q2. What are the different techniques to minimize congestion?
- Q3. What is useful skew, negative skew and positive skew?
DIGICOMM Semiconductor Physical Design Engineer Interview Experiences
2 interviews found
I applied via Approached by Company and was interviewed in Apr 2023. There were 2 interview rounds.
(8 Questions)
- Q1. What are the PD inputs and outputs
- Ans.
PD inputs are design specifications and constraints, while outputs are physical layout of the design.
Inputs include design specifications, constraints, technology libraries, and floorplan.
Outputs include physical layout, placement of components, routing of wires, and design verification.
Example: Input - RTL design, clock frequency, power constraints. Output - GDSII layout, timing analysis report.
- Q2. Describe each stage of PNR flow
- Ans.
PNR flow consists of synthesis, floorplanning, placement, clock tree synthesis, routing, and signoff stages.
Synthesis: Convert RTL code to gate-level netlist
Floorplanning: Define chip area, core, and I/O locations
Placement: Place gates in specific locations to meet timing constraints
Clock tree synthesis: Create clock distribution network
Routing: Connect gates with wires while considering timing and congestion
Signoff: V...
- Q3. What are the different techniques to minimize congestion?
- Ans.
Techniques to minimize congestion include buffer insertion, wire spreading, and layer assignment.
Buffer insertion: Adding buffers to critical paths to improve timing and reduce congestion.
Wire spreading: Distributing wires evenly to reduce congestion in specific areas.
Layer assignment: Properly assigning different signal layers to reduce congestion on a single layer.
- Q4. What is the setup and hold time and different techniques to fix the setup and hold time violations?
- Ans.
Setup and hold time are timing constraints in digital circuits. Techniques to fix violations include adjusting clock skew, buffering signals, and optimizing routing.
Setup time is the minimum amount of time a data input must be stable before the clock edge for proper operation.
Hold time is the minimum amount of time a data input must be stable after the clock edge for proper operation.
Techniques to fix setup and hold ti...
- Q5. What is signal integrity?
- Ans.
Signal integrity refers to the quality of an electrical signal as it travels through a circuit or system.
It involves ensuring that the signal remains clear and undistorted from the transmitter to the receiver.
Factors affecting signal integrity include impedance matching, noise, crosstalk, and reflections.
Signal integrity analysis is crucial in high-speed digital design to prevent data errors and ensure reliable communi...
- Q6. What is crosstalk and noise and how to fix it?
- Ans.
Crosstalk is unwanted interference between signals on adjacent lines, while noise is random unwanted signals that can degrade performance.
Crosstalk occurs when signals on adjacent lines interfere with each other due to coupling effects.
Noise is random unwanted signals that can be caused by various sources such as electromagnetic interference or power supply fluctuations.
To fix crosstalk, techniques like spacing out lin...
- Q7. What is clock latency, skew and jitter?
- Ans.
Clock latency is the delay between the clock signal being generated and reaching the destination, skew is the variation in arrival times of the clock signal at different destinations, and jitter is the variation in the period of the clock signal.
Clock latency is the delay between the clock signal being generated and reaching the destination.
Skew is the variation in arrival times of the clock signal at different destina...
- Q8. What is useful skew, negative skew and positive skew?
- Ans.
Useful skew, negative skew, and positive skew are terms used in physical design to describe timing constraints.
Useful skew refers to intentional delay added to certain paths to meet timing requirements.
Negative skew occurs when data arrives later than expected, leading to potential timing violations.
Positive skew occurs when data arrives earlier than expected, potentially causing setup time violations.
Skew can be adjus...
Interview Preparation Tips
- STATIC TIMING ANALYSIS
- Physical Design
- FORMAL VERIFICATION
- Physical Verification
Skills evaluated in this interview
I applied via Naukri.com and was interviewed in Sep 2021. There were 3 interview rounds.
Interview Questionnaire
2 Questions
- Q1. How to decide floor plan is good Or bad in the design
- Ans.
A good floor plan should optimize area, minimize congestion, and ensure signal integrity.
Optimize area utilization
Minimize congestion and routing complexity
Ensure signal integrity and minimize noise
Consider power and thermal constraints
Ensure ease of design changes and modifications
- Q2. What are the checks your do in offer post floor plan
- Ans.
Checks after floor plan in physical design engineering
Timing analysis to ensure timing constraints are met
Power analysis to ensure power constraints are met
Signal integrity analysis to ensure signal quality
Design rule check to ensure adherence to design rules
Physical verification to ensure layout is correct
Noise analysis to ensure noise constraints are met
Interview Preparation Tips
Physical Design Engineer Jobs at DIGICOMM Semiconductor
Top trending discussions
Interview questions from similar companies
Interview Preparation Tips
Experience: Written test for a duration of 1.5 hours
Test was based on VLSI design
Round: Interview
Experience: Technical and HR round are held together
Digital VLSI - Verilog skills, state machines, setup and hold time issues were tested
General Tips: Some questions in the test are repeated, so it might help to talk to a few people in advance
Questions are mainly related to VLSI mainly-Digital IC design, analog circuits
Skills: Verilog Skills, State Machines, Setup and Hold Times issues
College Name: IIT MADRAS
Design Engineer Interview Questions & Answers
Texas Instruments
Sai Vihari Chaturvedula
posted on 28 Aug 2016
I applied via Campus Placement
Interview Preparation Tips
Experience: Resume is not given any due importance in selection for further rounds . But honesty is very important as it counts once you are selected for HR round .
Tips: Try to be one hundred percent honest . And put your projects and course work in the beginning. They don't care your POR s and extra curricular activities.
Round: Test
Experience: Hardware - Questions are mainly from ELECTRICAL CIRCUITS (RLC ckts) , Analog ckts. Amplifiers , Opamps , digital system design . Aptitude section is very easy . Hardware section is tough .I felt Signal processing was easier , indeed I got selected for that profile .
Tips: Prepare thoroughly these courses :- EMC , DIGITAL SYSTEMS, NETWORKS AND SYSTEMS,ANALOG & DIGITAL SIGNAL PROCESSING , ANALOG CKTS COURSES .THAT SHOULD BE ENOUGH .
Duration: 90 - Signal Processing minutes
Total Questions: 120 - Hardware and aptitude
Round: Group Discussion
Experience: No
Tips: No
Duration: 2
College Name: IIT Madras
I applied via Recruitment Consulltant and was interviewed before Aug 2021. There was 1 interview round.
(2 Questions)
- Q1. What is aspect ratio?
- Ans.
Aspect ratio is the ratio of an object's width to its height.
Aspect ratio is commonly used in design and engineering to maintain proportionality.
It is often expressed as a ratio, such as 16:9 for a widescreen TV.
Aspect ratio can affect the visual perception and usability of a product.
It is important to consider aspect ratio when designing graphics or layouts for different devices or mediums.
- Q2. How do you decide stackup?
- Ans.
Stackup is decided based on the number of layers, signal integrity requirements, and manufacturing constraints.
Consider the number of layers required for the design
Evaluate signal integrity requirements and impedance control
Take into account manufacturing constraints such as minimum trace width and spacing
Balance cost and performance
Use simulation tools to optimize the stackup
Consult with PCB fabricators for their reco
Interview Preparation Tips
Interview Preparation Tips
Experience: The selection procedure is a test followed by tech interview and an HR interview.
The test had two parts:
Aptitude (common across all profiles)
A tech. test (separate for each profile)
Round: Interview
Experience: The tech interview was the important one and the HR interview was just about knowing the student and vice-versa. The tech interview was more concentrated on the basics and more importance was given to the approach of solving the problem rather than solving the problem itself.
No CGPA cutoff.
Round: Interview
Experience: Not very important.
General Tips: The work is well structured and executed. There is a lot of opportunity for more technical learning. Interns are also included into the teams and this helps the intern on knowing about the things going around them and gets an overall view of how things work.
As a whole, the work is very good, and exceeds all the expectations of the students.
College Name: IIT Madras
Selected
I applied via Referral and was interviewed before Mar 2023. There were 3 interview rounds.
(1 Question)
- Q1. Explain functional and code coverage.
- Ans.
Functional coverage ensures all functions are tested, while code coverage ensures all lines of code are executed.
Functional coverage focuses on testing the functionality of the design.
Code coverage ensures that all lines of code are executed during testing.
Functional coverage helps in identifying missing or incomplete functionality.
Code coverage helps in identifying untested code paths.
Example: Functional coverage may ...
(1 Question)
- Q1. Questions on AHB protocol.
(1 Question)
- Q1. Digital design based questions.
Skills evaluated in this interview
Process Engineer Interview Questions & Answers
TDK India Private Limited
Anonymous
posted on 18 Sep 2023
Selected
I applied via Naukri.com and was interviewed in Aug 2023. There were 4 interview rounds.
(3 Questions)
- Q1. What is this kaizen and suggestion
- Ans.
Kaizen is a Japanese term for continuous improvement, while suggestion refers to ideas or proposals for improvement.
Kaizen focuses on making small, incremental improvements in processes or systems
Suggestion involves offering ideas or proposals for improvement to enhance efficiency or quality
Kaizen and suggestion are key components of continuous improvement initiatives in organizations
Examples of kaizen include implemen...
- Q2. What is this oee calculation
- Ans.
OEE (Overall Equipment Effectiveness) is a measure of how well a manufacturing process is performing.
OEE is calculated by multiplying Availability, Performance, and Quality percentages.
Availability is the ratio of actual production time to planned production time.
Performance is the ratio of actual production speed to ideal production speed.
Quality is the ratio of good units produced to total units produced.
OEE provides...
- Q3. What is this PPLH improvement
- Ans.
PPLH improvement refers to the process of improving productivity, profitability, lead time, and quality in a manufacturing setting.
PPLH stands for Productivity, Profitability, Lead Time, and Quality in a manufacturing process.
Improving PPLH involves optimizing production processes, reducing waste, enhancing efficiency, and ensuring high product quality.
Examples of PPLH improvement strategies include implementing lean m...
(3 Questions)
- Q1. Tell me about your self
- Q2. What's is this 5s and shop floor
- Ans.
5S is a methodology for organizing a workplace for efficiency and effectiveness. Shop floor refers to the area where production or manufacturing takes place.
5S stands for Sort, Set in Order, Shine, Standardize, and Sustain.
It involves organizing the workplace to eliminate waste, improve efficiency, and ensure safety.
Examples include labeling tools and equipment, creating designated storage areas, and implementing regul...
- Q3. What is this tpm and tqm
- Ans.
TPM stands for Total Productive Maintenance and TQM stands for Total Quality Management.
TPM focuses on maximizing the efficiency of equipment and machinery to prevent breakdowns and defects.
TQM focuses on improving the quality of products and processes through continuous improvement and customer satisfaction.
Both TPM and TQM aim to optimize production processes and reduce waste.
Examples of TPM activities include regula...
(4 Questions)
- Q1. Manpower power handling
- Q2. What do you rejection analysis
- Ans.
Rejection analysis involves identifying and addressing the root causes of rejected products or processes.
Identify the specific reasons for rejection, such as defects in materials, design flaws, or manufacturing errors
Collect data and analyze trends to determine common issues leading to rejection
Implement corrective actions to address the root causes and prevent future rejections
Monitor the effectiveness of the correcti...
- Q3. What do you production planing
- Q4. What do you all documents updated i KPI instruction bord
Interview Preparation Tips
govekar prajwal
(1 Question)
- Q1. Introduction about ourselves
(1 Question)
- Q1. Personal interview ( personality test )
I applied via Naukri.com and was interviewed in Apr 2024. There was 1 interview round.
(1 Question)
- Q1. Electronic related questions were asked PCB related
DIGICOMM Semiconductor Interview FAQs
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DIGICOMM Semiconductor Physical Design Engineer Interview Process
based on 1 interview
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DIGICOMM Semiconductor Physical Design Engineer Reviews and Ratings
based on 13 reviews
Rating in categories
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Physical Design Engineer
41
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|  ₹2.5 L/yr - ₹11.9 L/yr |
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| ₹1.8 L/yr - ₹8 L/yr |
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| ₹5 L/yr - ₹16 L/yr |
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