i
SmartSoC Solutions
Filter interviews by
I applied via LinkedIn and was interviewed in Nov 2024. There were 3 interview rounds.
It was good and easy as well
Polymorphism is the ability of a function or method to behave differently based on the object it is called with.
Polymorphism allows objects of different classes to be treated as objects of a common superclass.
There are two types of polymorphism: compile-time (method overloading) and runtime (method overriding).
Example: Animal superclass with methods like eat() and sleep(), and subclasses like Dog and Cat that override
I applied via LinkedIn and was interviewed before Mar 2023. There were 3 interview rounds.
SmartSoC Solutions interview questions for popular designations
I applied via Walk-in and was interviewed before Jun 2023. There was 1 interview round.
That was easy actually
I applied via Campus Placement and was interviewed in Aug 2022. There were 4 interview rounds.
Aptitude round consists of digital electronics,c programming, aptitude and mpmc
these questions are not tough but you have to score max for to shortlist.
Yes, I am willing to relocate for the right opportunity.
I am open to exploring new locations and cultures
I understand that relocation may be necessary for career growth
I am willing to make the necessary arrangements and adjustments for relocation
Smartsoc company offers unique opportunities for growth and learning in the embedded field.
Smartsoc company has a strong reputation in the industry for its innovative embedded solutions.
They provide a supportive and collaborative work environment for trainee engineers.
Working at Smartsoc offers exposure to cutting-edge technologies and projects.
The company has a track record of successfully training and mentoring train...
I applied via campus placement at Laki Reddy Bali Reddy College of Engineering, Krishna and was interviewed in Sep 2022. There were 2 interview rounds.
Structured exam by which we can have a fair screening
A higher order multiplexer can be designed by cascading lower order ones.
Start by designing a 2:1 multiplexer using logic gates
Cascading multiple 2:1 multiplexers can create a higher order multiplexer
For example, two 2:1 multiplexers can be cascaded to create a 4:1 multiplexer
To reduce propagation delay of adder circuit, use faster logic gates, reduce wire length, and optimize layout.
Use faster logic gates like CMOS instead of TTL
Reduce wire length to minimize capacitance
Optimize layout to minimize signal path length and reduce parasitic capacitance
I applied via Naukri.com and was interviewed in Aug 2021. There was 1 interview round.
To catch a missing tie cell issue using calibre, run DRC check with appropriate rule deck.
Create a rule deck with tie cell rules
Run DRC check using the rule deck
Check the DRC report for any missing tie cell violations
Fix the violations and re-run DRC check
Repeat until all violations are fixed
Top trending discussions
posted on 31 Dec 2024
I was interviewed in Dec 2024.
Interview experience
based on 71 reviews
Rating in categories
Physical Design Engineer
30
salaries
| ₹2 L/yr - ₹9.5 L/yr |
Senior Engineer
27
salaries
| ₹9 L/yr - ₹25 L/yr |
Verification Engineer
19
salaries
| ₹7.6 L/yr - ₹15.4 L/yr |
Design & Verification Engineer
10
salaries
| ₹4.5 L/yr - ₹12 L/yr |
Embedded Engineer
9
salaries
| ₹3.5 L/yr - ₹12.4 L/yr |
TCS
Infosys
Wipro
HCLTech