SmartSoC Solutions Physical Design Engineer Interview Questions and Answers

Q1. Explain the PD flow?
Ans. 
PD flow is the process of designing and implementing the physical layout of an integrated circuit.
• PD flow involves floorplanning, placement, routing, and physical verification.

• Floorplanning determines the placement of blocks and macros on the chip.

• Placement involves placing standard cells in the available space based on timing and area constraints.

• Routing connects the placed cells using metal layers to create the final...read more
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Q2. Asked related to floor planning ?
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Q3. How to fix antenna violation?
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Antenna violations can be fixed by adjusting the metal layers, adding shielding, or changing the routing.
• Adjust metal layers to increase spacing between antennas

• Add shielding to isolate antennas from each other

• Change routing to avoid crossing antennas
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Q1. Sv hvm questions on constraiants and assertions
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Q2. Questions on resume projects
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Q1. Questions on protocols
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Q2. Sv uvm questions
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Q1. Salary and pckge discussion
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Q2. Details on client interview
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Q1. Projects and challenges
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Q2. Sv uvm basics
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Q1. Toggle the bits of given input
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Toggle the bits of given input
• Create a mask with all bits set to 1

• XOR the input with the mask to toggle the bits

• Repeat the process for each bit position
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Q2. Clear the set bit
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Q1. Print the star pattern
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Print a star pattern using loops
• Use nested loops to print the desired pattern

• Increment the number of stars in each row to create the pattern

• Example: for a pattern with 5 rows - * , ** , *** , **** , *****
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Q2. Microprocessor microcontroller topics are asked
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Q1. They asked from Digital, COA
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Q1. They asked the concepts of COA
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Q1. First started with Puzzle and then about company
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Q1. Simple FSM given similar to mux and asked for testcases and assertions.
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Q2. Coverage to write transitions of states.
Ans. 
Coverage-driven verification techniques are used to ensure all possible state transitions are exercised.
• Coverage metrics like state, transition, and toggle coverage can be used to track the completeness of state transitions.

• Writing directed tests to cover specific state transitions can help achieve higher coverage.

• Random stimulus generation can also be used to explore different state transitions.

• Functional coverage can...read more
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Q1. Basics of analog , digital and vlsi
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Q2. On face to face interview, they asked me abt my projects , digital, little analog , vlsi ( verilog), microcontrollers and c programming
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40 aptitude qns and some mcqs on basic programming

Q1. I was asked to write two sum, palindrome function and merge sort code in whatever language I'm comfortable in
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Q2. Two sum- return true or false
Ans. 
Given an array of integers, determine if there are two numbers that add up to a specific target.
• Iterate through the array and store each element in a hash set.

• For each element, check if the difference between the target and the element exists in the hash set.

• If the difference exists, return true; otherwise, continue iterating.

• Example: nums = [2, 7, 11, 15], target = 9. The function should return true as 2 + 7 = 9.
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Q3. Merge sort function code
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Q4. Palindromic string or not
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Q1. Asked the working experience and the related skills to the new job
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Q1. Coding questions in Verilog, Systemverilog, random constraints such as how to write a onehot in different ways
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Q1. Asked the expectation of the base salary and overall compensation
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