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SmartSoC Solutions Physical Design Engineer Interview Questions and Answers
SmartSoC Solutions Physical Design Engineer Interview Experiences
1 interview found
I applied via Naukri.com and was interviewed in Aug 2021. There was 1 interview round.
Interview Questionnaire
1 Question
- Q1. How to catch a missing tie cell issue using calibre ?
- Ans.
To catch a missing tie cell issue using calibre, run DRC check with appropriate rule deck.
Create a rule deck with tie cell rules
Run DRC check using the rule deck
Check the DRC report for any missing tie cell violations
Fix the violations and re-run DRC check
Repeat until all violations are fixed
Interview Preparation Tips
Skills evaluated in this interview
Top trending discussions
Interview questions from similar companies
(1 Question)
- Q1. Sdc basics TCL coding
I applied via Campus Placement and was interviewed in Aug 2024. There were 3 interview rounds.
Aotitude,core que on all subjects in ece
(2 Questions)
- Q1. INTERNSHIP EXPERIENCE
- Ans.
I completed a 6-month internship at XYZ Company where I gained hands-on experience in physical design tools and methodologies.
Worked on floorplanning, placement, and routing of digital designs
Utilized tools such as Cadence Innovus and Synopsys ICC
Collaborated with cross-functional teams to optimize design performance
- Q2. ON DSD,VLSI,ANALOG ELECTRONICS
(2 Questions)
- Q1. APTITUDE,MATH,VLSI,DSD
- Q2. VLSI (HARD QUESTION BASED ON INDUSTRY LEVEL LIKE ON CIRCUIT HE GIVES ONE SCENARIO U HAVE TO ANSWER IT)
Interview Preparation Tips
(1 Question)
- Q1. Congestion analysis
(2 Questions)
- Q1. What is cross talk
- Ans.
Cross talk is the unwanted transfer of signals between different components or traces on a circuit board.
Occurs when signals from one trace interfere with signals on another trace
Can lead to signal distortion or errors in data transmission
Prevented by proper spacing and shielding between traces
Example: Cross talk between data lines on a PCB causing errors in communication
- Q2. How to define generated clocks through edges
- Ans.
Generated clocks through edges are defined by specifying the source clock and the edge on which the generated clock is based.
Specify the source clock for the generated clock
Define the edge (rising/falling) on which the generated clock is based
Use tools like Synopsys Design Compiler to define generated clocks
I applied via Recruitment Consulltant and was interviewed in Sep 2023. There was 1 interview round.
(2 Questions)
- Q1. Temperature of the design you worked for?
- Ans.
The temperature of the design I worked on was optimized to ensure proper functionality and reliability.
The temperature was carefully controlled to prevent overheating and ensure performance.
Thermal analysis was conducted to determine the optimal operating temperature.
Cooling solutions such as heat sinks or fans were implemented to manage heat dissipation.
Examples: The design operated within a temperature range of 0-70 ...
- Q2. Mention the corners you worked in
Interview Preparation Tips
Skills evaluated in this interview
Interview Preparation Tips
Experience: The selection procedure is a test followed by tech interview and an HR interview.
The test had two parts:
Aptitude (common across all profiles)
A tech. test (separate for each profile)
Round: Interview
Experience: The tech interview was the important one and the HR interview was just about knowing the student and vice-versa. The tech interview was more concentrated on the basics and more importance was given to the approach of solving the problem rather than solving the problem itself.
No CGPA cutoff.
Round: Interview
Experience: Not very important.
General Tips: The work is well structured and executed. There is a lot of opportunity for more technical learning. Interns are also included into the teams and this helps the intern on knowing about the things going around them and gets an overall view of how things work.
As a whole, the work is very good, and exceeds all the expectations of the students.
College Name: IIT Madras
Electrical Design Engineer Interview Questions & Answers
Applied Materials
Anonymous
posted on 29 Oct 2017
I applied via Recruitment Consultant and was interviewed in Mar 2017. There were 2 interview rounds.
Interview Preparation Tips
Experience: Verified the kind of work which I do and they told about their expectations.
General Tips: Had a final round of discussion with the US team member.
Skills: Communication, Problem Solving, Analytical Skills, Leadership, Presentation Skills, Decision Making Skills
Duration: 1-4 weeks
Design Engineer Interview Questions & Answers
Texas Instruments
Sai Vihari Chaturvedula
posted on 28 Aug 2016
I applied via Campus Placement
Interview Preparation Tips
Experience: Resume is not given any due importance in selection for further rounds . But honesty is very important as it counts once you are selected for HR round .
Tips: Try to be one hundred percent honest . And put your projects and course work in the beginning. They don't care your POR s and extra curricular activities.
Round: Test
Experience: Hardware - Questions are mainly from ELECTRICAL CIRCUITS (RLC ckts) , Analog ckts. Amplifiers , Opamps , digital system design . Aptitude section is very easy . Hardware section is tough .I felt Signal processing was easier , indeed I got selected for that profile .
Tips: Prepare thoroughly these courses :- EMC , DIGITAL SYSTEMS, NETWORKS AND SYSTEMS,ANALOG & DIGITAL SIGNAL PROCESSING , ANALOG CKTS COURSES .THAT SHOULD BE ENOUGH .
Duration: 90 - Signal Processing minutes
Total Questions: 120 - Hardware and aptitude
Round: Group Discussion
Experience: No
Tips: No
Duration: 2
College Name: IIT Madras
I applied via Naukri.com and was interviewed in Apr 2024. There was 1 interview round.
(1 Question)
- Q1. Electronic related questions were asked PCB related
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SmartSoC Solutions Physical Design Engineer Reviews and Ratings
based on 7 reviews
Rating in categories
|
Physical Design Engineer
33
salaries
|  ₹2 L/yr - ₹7.8 L/yr |
|
Senior Engineer
29
salaries
| ₹9 L/yr - ₹25 L/yr |
|
Verification Engineer
21
salaries
| ₹7.2 L/yr - ₹20.4 L/yr |
|
Design & Verification Engineer
14
salaries
| ₹4.5 L/yr - ₹12 L/yr |
|
RTL Design Engineer
9
salaries
| ₹7 L/yr - ₹14 L/yr |
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