SmartSoC Solutions Verification Engineer Interview Questions and Answers

Q1. Basics of analog , digital and vlsi
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Q2. On face to face interview, they asked me abt my projects , digital, little analog , vlsi ( verilog), microcontrollers and c programming
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Q1. The question was draw cmos inverter transfer characteristics and by varying some parameters they asked their effects on it.
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Q1. Asked the working experience and the related skills to the new job
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Q1. Coding questions in Verilog, Systemverilog, random constraints such as how to write a onehot in different ways
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Q1. Asked the expectation of the base salary and overall compensation
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Q1. About SV and UVM mainly and some questions from projects
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Q1. Mainly questions from Projects and coding
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Q2. Write code for Hend shake in UVM
Ans. 
Code for Handshake in UVM
• Create a sequence item for handshake

• Use a sequence to drive the handshake

• Implement the handshake protocol in the driver and monitor

• Use analysis ports to check for successful handshake
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Q1. What are your salary expectations?
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Q1. Toggle the bits of given input
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Toggle the bits of given input
• Create a mask with all bits set to 1

• XOR the input with the mask to toggle the bits

• Repeat the process for each bit position
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Q2. Clear the set bit
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Q1. Print the star pattern
Ans. 
Print a star pattern using loops
• Use nested loops to print the desired pattern

• Increment the number of stars in each row to create the pattern

• Example: for a pattern with 5 rows - * , ** , *** , **** , *****
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Q2. Microprocessor microcontroller topics are asked
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Basic aptitude-10 question,digital moderate -Question,analog moderate -10 question,verilog and system verilog -10 question

Q1. Latches and flip flop all characteristics equation and proof of the characteristics equation in flip flop.applications of flip flop
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Q2. OOPS,INHERITANCE,VERILOG,BLOCKING - NON BLOCKING ASSIGNMENT OPERATOR and all the basic operations of verilog .
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Q3. Discussion on work experience.
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I have done internship in Moschip Institute of Silicon Systems.

Q1. Basic questions on Digital Electronics, Verilog, System Verilog and UVM.
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Q2. What is m_sequencer and p_sequencer?
Ans. 
m_sequencer and p_sequencer are components used in design and verification for sequencing operations.
• m_sequencer and p_sequencer are commonly used in digital design for controlling the sequence of operations.

• m_sequencer typically refers to a master sequencer, while p_sequencer refers to a peripheral sequencer.

• These components are often used in verification environments to ensure proper sequencing of events.

• For example,...read more
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Q3. What is factory override in UVM?
Ans. 
Factory override in UVM allows users to replace default factory methods with custom implementations.
• Factory override is used to customize the behavior of UVM components without modifying the original source code.

• It allows users to replace default factory methods with custom implementations to meet specific requirements.

• Factory override can be useful for debugging, testing, or adding new features to existing UVM compone...read more
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Q4. What is the call back in UVM?
Ans. 
A call back in UVM is a mechanism used to notify a component about a specific event or condition.
• A call back is defined using a function or task in the UVM component.

• It is registered with the UVM framework to be executed when a certain event occurs.

• Call backs are commonly used for handling events like transaction completion or error detection.
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Q5. Questions relatedto ethernet project?
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