DIGICOMM Semiconductor Verification Engineer Interview Questions and Answers

Q1. The question was draw cmos inverter transfer characteristics and by varying some parameters they asked their effects on it.
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Q1. Asked the working experience and the related skills to the new job
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Q1. Coding questions in Verilog, Systemverilog, random constraints such as how to write a onehot in different ways
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Q1. Asked the expectation of the base salary and overall compensation
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Q1. Related to verification
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Q2. Related to verification
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Q1. Related to verification
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Q1. Is setup and hold uncertainty values are different
Ans. 
Yes, setup and hold uncertainty values are different in physical design engineering.
• Setup uncertainty is related to the arrival time of the data signal at the input of the flip-flop, while hold uncertainty is related to the removal time of the data signal.

• Setup time is the minimum amount of time the data input must be stable before the clock edge, while hold time is the minimum amount of time the data input must be sta...read more
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Q1. What is an ICG? How would you use it in the design?
Ans. 
ICG stands for Inter-Chip Global. It is a network that connects multiple chips in a system.
• ICG is used to transfer data between different chips in a system

• It helps in reducing the number of wires required for communication between chips

• ICG can be used in various design aspects such as clock distribution, power management, and data transfer

• Example: In a multi-chip system, ICG can be used to transfer clock signals from o
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Q2. How will MSCTS help at SOC level CTS
Ans. 
MSCTS can help in achieving better clock distribution and reducing skew at SOC level CTS.
• MSCTS (Multi-Source Clock Tree Synthesis) can optimize the clock tree for better skew and jitter performance.

• It can also help in reducing power consumption by optimizing the clock network.

• MSCTS can handle multiple clock sources and ensure proper synchronization.

• It can also help in meeting timing constraints and reducing clock tree ...read more
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Q1. What was the most difficult challenge faced in the projects you worked?
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Q2. How will you fix setup and hold time when both are violating at the same time.
Ans. 
Fixing setup and hold time violations simultaneously requires adjusting clock timing and/or data path delays.
• Identify the critical path causing the violations

• Adjust the clock timing to meet setup and hold requirements

• Adjust the data path delays to meet setup and hold requirements

• Use tools like static timing analysis and delay calculation to determine necessary adjustments

• Iteratively adjust timing and delays until viola
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Mcq questions based on aptitude(a bit ) and digital design, VLSI, Clock related questions

Q1. Had 4 technical interview rounds, Face-to face in Microchip Office 1st round - digital electronics based + coding(verilog or Vhdl) 2nd round - analog, microcontrollers, Digital electronics based questions ...read more
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Q1. Design of mux and ff
Ans. 
A multiplexer (mux) is a digital circuit that selects one of several input signals and forwards it to a single output. A flip-flop (ff) is a type of latch circuit that stores a single bit of data.
• Mux design involves selecting one of multiple input signals based on a control signal

• FF design involves storing a single bit of data using a clock signal

• Mux can be implemented using logic gates like AND, OR, and NOT gates

• FF ca...read more
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Q2. Basics of sv n verilog
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Q3. Sta question about timing violation
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Q4. Thesis related question
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Q5. Some basic design question
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