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Yes, setup and hold uncertainty values are different in physical design engineering.
Setup uncertainty is related to the arrival time of the data signal at the input of the flip-flop, while hold uncertainty is related to the removal time of the data signal.
Setup time is the minimum amount of time the data input must be stable before the clock edge, while hold time is the minimum amount of time the data input must be sta...
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I applied via Campus Placement and was interviewed in Aug 2024. There were 3 interview rounds.
Aotitude,core que on all subjects in ece
I completed a 6-month internship at XYZ Company where I gained hands-on experience in physical design tools and methodologies.
Worked on floorplanning, placement, and routing of digital designs
Utilized tools such as Cadence Innovus and Synopsys ICC
Collaborated with cross-functional teams to optimize design performance
Cross talk is the unwanted transfer of signals between different components or traces on a circuit board.
Occurs when signals from one trace interfere with signals on another trace
Can lead to signal distortion or errors in data transmission
Prevented by proper spacing and shielding between traces
Example: Cross talk between data lines on a PCB causing errors in communication
Generated clocks through edges are defined by specifying the source clock and the edge on which the generated clock is based.
Specify the source clock for the generated clock
Define the edge (rising/falling) on which the generated clock is based
Use tools like Synopsys Design Compiler to define generated clocks
posted on 1 Nov 2022
I applied via Referral and was interviewed before Nov 2021. There were 2 interview rounds.
posted on 29 Nov 2024
Toggle the bits of given input
Create a mask with all bits set to 1
XOR the input with the mask to toggle the bits
Repeat the process for each bit position
Print a star pattern using loops
Use nested loops to print the desired pattern
Increment the number of stars in each row to create the pattern
Example: for a pattern with 5 rows - * , ** , *** , **** , *****
posted on 29 Feb 2024
I applied via Campus Placement and was interviewed in Jan 2024. There was 1 interview round.
I applied via LinkedIn and was interviewed in Oct 2023. There were 2 interview rounds.
40 aptitude qns and some mcqs on basic programming
Given an array of integers, determine if there are two numbers that add up to a specific target.
Iterate through the array and store each element in a hash set.
For each element, check if the difference between the target and the element exists in the hash set.
If the difference exists, return true; otherwise, continue iterating.
Example: nums = [2, 7, 11, 15], target = 9. The function should return true as 2 + 7 = 9.
posted on 15 Apr 2024
I applied via Referral and was interviewed before Apr 2023. There were 3 interview rounds.
I applied via Referral and was interviewed before Jan 2022. There were 3 interview rounds.
Mostly on TB components coding, different scenario coding..
Mostly on past project experience, different implementation on those projects.
Seeking new challenges and growth opportunities in the field of verification engineering.
Desire to work on more complex projects
Opportunity to learn and apply new technologies
Seeking a more collaborative and supportive work environment
Career advancement and professional development
Company restructuring or downsizing
Relocation or commute concerns
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