Mirafra Technologies Physical Design Engineer Interview Questions and Answers

Aotitude,core que on all subjects in ece

Q1. INTERNSHIP EXPERIENCE
Ans. 
I completed a 6-month internship at XYZ Company where I gained hands-on experience in physical design tools and methodologies.
• Worked on floorplanning, placement, and routing of digital designs

• Utilized tools such as Cadence Innovus and Synopsys ICC

• Collaborated with cross-functional teams to optimize design performance
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Q2. ON DSD,VLSI,ANALOG ELECTRONICS
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Q1. APTITUDE,MATH,VLSI,DSD
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Q2. VLSI (HARD QUESTION BASED ON INDUSTRY LEVEL LIKE ON CIRCUIT HE GIVES ONE SCENARIO U HAVE TO ANSWER IT)
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Q1. Is setup and hold uncertainty values are different
Ans. 
Yes, setup and hold uncertainty values are different in physical design engineering.
• Setup uncertainty is related to the arrival time of the data signal at the input of the flip-flop, while hold uncertainty is related to the removal time of the data signal.

• Setup time is the minimum amount of time the data input must be stable before the clock edge, while hold time is the minimum amount of time the data input must be sta...read more
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Q1. What are the PD inputs and outputs
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PD inputs are design specifications and constraints, while outputs are physical layout of the design.
• Inputs include design specifications, constraints, technology libraries, and floorplan.

• Outputs include physical layout, placement of components, routing of wires, and design verification.

• Example: Input - RTL design, clock frequency, power constraints. Output - GDSII layout, timing analysis report.
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Q2. Describe each stage of PNR flow
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PNR flow consists of synthesis, floorplanning, placement, clock tree synthesis, routing, and signoff stages.
• Synthesis: Convert RTL code to gate-level netlist

• Floorplanning: Define chip area, core, and I/O locations

• Placement: Place gates in specific locations to meet timing constraints

• Clock tree synthesis: Create clock distribution network

• Routing: Connect gates with wires while considering timing and congestion

• Signoff: V...read more
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Q3. What are the different techniques to minimize congestion?
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Techniques to minimize congestion include buffer insertion, wire spreading, and layer assignment.
• Buffer insertion: Adding buffers to critical paths to improve timing and reduce congestion.

• Wire spreading: Distributing wires evenly to reduce congestion in specific areas.

• Layer assignment: Properly assigning different signal layers to reduce congestion on a single layer.
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Q4. What is the setup and hold time and different techniques to fix the setup and hold time violations?
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Setup and hold time are timing constraints in digital circuits. Techniques to fix violations include adjusting clock skew, buffering signals, and optimizing routing.
• Setup time is the minimum amount of time a data input must be stable before the clock edge for proper operation.

• Hold time is the minimum amount of time a data input must be stable after the clock edge for proper operation.

• Techniques to fix setup and hold ti...read more
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Q5. What is signal integrity?
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Signal integrity refers to the quality of an electrical signal as it travels through a circuit or system.
• It involves ensuring that the signal remains clear and undistorted from the transmitter to the receiver.

• Factors affecting signal integrity include impedance matching, noise, crosstalk, and reflections.

• Signal integrity analysis is crucial in high-speed digital design to prevent data errors and ensure reliable communi...read more
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Q6. What is crosstalk and noise and how to fix it?
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Crosstalk is unwanted interference between signals on adjacent lines, while noise is random unwanted signals that can degrade performance.
• Crosstalk occurs when signals on adjacent lines interfere with each other due to coupling effects.

• Noise is random unwanted signals that can be caused by various sources such as electromagnetic interference or power supply fluctuations.

• To fix crosstalk, techniques like spacing out lin...read more
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Q7. What is clock latency, skew and jitter?
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Clock latency is the delay between the clock signal being generated and reaching the destination, skew is the variation in arrival times of the clock signal at different destinations, and jitter is the variation in the period of the clock signal.
• Clock latency is the delay between the clock signal being generated and reaching the destination.

• Skew is the variation in arrival times of the clock signal at different destina...read more
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Q8. What is useful skew, negative skew and positive skew?
Ans. 
Useful skew, negative skew, and positive skew are terms used in physical design to describe timing constraints.
• Useful skew refers to intentional delay added to certain paths to meet timing requirements.

• Negative skew occurs when data arrives later than expected, leading to potential timing violations.

• Positive skew occurs when data arrives earlier than expected, potentially causing setup time violations.

• Skew can be adjus...read more
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Q1. What is an ICG? How would you use it in the design?
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ICG stands for Inter-Chip Global. It is a network that connects multiple chips in a system.
• ICG is used to transfer data between different chips in a system

• It helps in reducing the number of wires required for communication between chips

• ICG can be used in various design aspects such as clock distribution, power management, and data transfer

• Example: In a multi-chip system, ICG can be used to transfer clock signals from o
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Q2. How will MSCTS help at SOC level CTS
Ans. 
MSCTS can help in achieving better clock distribution and reducing skew at SOC level CTS.
• MSCTS (Multi-Source Clock Tree Synthesis) can optimize the clock tree for better skew and jitter performance.

• It can also help in reducing power consumption by optimizing the clock network.

• MSCTS can handle multiple clock sources and ensure proper synchronization.

• It can also help in meeting timing constraints and reducing clock tree ...read more
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Q1. What was the most difficult challenge faced in the projects you worked?
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Q2. How will you fix setup and hold time when both are violating at the same time.
Ans. 
Fixing setup and hold time violations simultaneously requires adjusting clock timing and/or data path delays.
• Identify the critical path causing the violations

• Adjust the clock timing to meet setup and hold requirements

• Adjust the data path delays to meet setup and hold requirements

• Use tools like static timing analysis and delay calculation to determine necessary adjustments

• Iteratively adjust timing and delays until viola
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Q1. Basic MOS fundamentals and basic knowledge of high speed VLSI circuit design knowledge and how to optimize circuit for PPA metric.
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Q1. VLSI fundamentals.
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Q1. Asked the working experience and the related skills to the new job
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Q1. Coding questions in Verilog, Systemverilog, random constraints such as how to write a onehot in different ways
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Q1. Asked the expectation of the base salary and overall compensation
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Q1. How to integrate and differentiate signals through software embedded c for 8 bit , 16 bit architecture
Ans. 
Integrating and differentiating signals through software embedded C for 8-bit and 16-bit architecture involves utilizing appropriate data types and algorithms.
• Use fixed-point arithmetic for 8-bit architecture to maintain precision

• Leverage floating-point arithmetic for 16-bit architecture for higher precision

• Implement algorithms like finite difference method for differentiation

• Utilize digital signal processing technique...read more
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Q2. How to implement digital filter through software
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Digital filters can be implemented through software by using algorithms such as Finite Impulse Response (FIR) or Infinite Impulse Response (IIR).
• Choose the appropriate filter type based on the desired frequency response and computational complexity

• Implement the filter algorithm in the firmware code using programming languages like C or assembly

• Optimize the filter design for efficient memory usage and processing speed

• Te...read more
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Q1. About SV and UVM mainly and some questions from projects
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Q1. Mainly questions from Projects and coding
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Q2. Write code for Hend shake in UVM
Ans. 
Code for Handshake in UVM
• Create a sequence item for handshake

• Use a sequence to drive the handshake

• Implement the handshake protocol in the driver and monitor

• Use analysis ports to check for successful handshake
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Q1. What are your salary expectations?
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