MediaTek India Technology VLSI Design and Verification Engineer Interview Questions and Answers

Q1. Write code randc behaviour
Ans. 
randc behavior generates random complex numbers with specified distribution
• Use randc to generate random complex numbers

• Specify distribution using arguments like mean, variance, etc.

• Example: randc(10, 1, 2) generates 10 random complex numbers with mean 1 and variance 2
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Q2. Functinal coverage
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Q3. Code coverage related questions
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Q4. Monitor and scoreboard connections
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Q5. Project related questions
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Q1. Basics of analog , digital and vlsi
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Q2. On face to face interview, they asked me abt my projects , digital, little analog , vlsi ( verilog), microcontrollers and c programming
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Q1. The question was draw cmos inverter transfer characteristics and by varying some parameters they asked their effects on it.
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Q1. Asked the working experience and the related skills to the new job
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Q1. Coding questions in Verilog, Systemverilog, random constraints such as how to write a onehot in different ways
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Q1. Asked the expectation of the base salary and overall compensation
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Q1. FSMs, Caches, Mealy, Moore
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Q2. Caches, verilog, basic coding, d_flip_flop
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Q1. Plans for the future?
Ans. 
I plan to continue advancing my skills in design verification engineering and eventually move into a leadership role.
• Continue taking relevant courses and certifications to stay updated on industry trends

• Seek opportunities to lead projects and teams to gain leadership experience

• Network with professionals in the field to learn from their experiences and insights
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50 questions for 90 mins

Q1. Basic digital electronics ,static time analysis, verilog coding , basic c programing
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