Filter interviews by
I applied via Referral and was interviewed in Jun 2022. There were 2 interview rounds.
All topics of reasoning and mathematics
Counters are digital circuits that count the number of clock cycles or events that occur within a system.
Synchronous counters use a common clock signal to synchronize the counting process.
Asynchronous counters use individual clock signals for each flip-flop, allowing for more flexibility in counting sequences.
Synchronous counters are faster and more reliable, but require a stable clock signal.
Asynchronous counters are ...
I applied via Naukri.com and was interviewed in May 2022. There were 2 interview rounds.
I am currently working at XYZ Company as an R&D Engineer with a CTC of $X.
Currently working at XYZ Company
Position: R&D Engineer
CTC: $X
I have experience with various working methods and skills in R&D engineering.
Proficient in conducting research and analysis to develop innovative solutions
Skilled in using CAD software for designing and prototyping
Experienced in conducting experiments and tests to validate hypotheses
Knowledgeable in data analysis and statistical techniques
Familiar with project management methodologies and tools
Strong problem-solving an
I applied via Naukri.com and was interviewed before Sep 2022. There were 3 interview rounds.
posted on 3 Sep 2024
I applied via Naukri.com and was interviewed in Aug 2024. There were 3 interview rounds.
25 Questions were given on the Solidworks software
posted on 13 Nov 2024
CDC stands for Clock Domain Crossing technique used in digital design to ensure proper data transfer between different clock domains.
CDC technique involves synchronizing data signals when crossing between different clock domains to prevent metastability issues.
It is necessary because different clock domains operate at different frequencies and can lead to data corruption if not properly synchronized.
Common CDC techniqu...
Transfer multiple bits in CDC involves using a parallel data transfer method.
Use parallel data transfer method to transfer multiple bits simultaneously
Implement a shift register to store and shift out multiple bits
Utilize multiplexers to select and transfer specific bits
Consider using a bus architecture for efficient data transfer
posted on 3 Oct 2023
I applied via Job Portal and was interviewed in Apr 2023. There were 4 interview rounds.
3 HackerEarth Qestions in 1 hour.
1 easy
2 medium
posted on 16 May 2023
I applied via Referral and was interviewed in Nov 2022. There were 2 interview rounds.
I applied via Campus Placement and was interviewed before Jun 2023. There were 2 interview rounds.
posted on 16 Sep 2021
I applied via Naukri.com and was interviewed in Mar 2021. There was 1 interview round.
based on 9 reviews
Rating in categories
R&D Engineer
96
salaries
| ₹4.8 L/yr - ₹18 L/yr |
Module Lead
33
salaries
| ₹6.5 L/yr - ₹24 L/yr |
RTL Design Engineer
18
salaries
| ₹7.5 L/yr - ₹20 L/yr |
Senior R&D Engineer
10
salaries
| ₹11.3 L/yr - ₹18 L/yr |
Verification Engineer
8
salaries
| ₹6 L/yr - ₹18.5 L/yr |
Accurex Biomedical
Capgemini Engineering
Persistent Systems
TCS