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RTL code for FIFO is a hardware description language code that implements a First-In-First-Out buffer.
Use Verilog or VHDL to write RTL code for FIFO
Define input and output ports for data and control signals
Implement logic for enqueue and dequeue operations
Use registers or memory elements to store data temporarily
Writing 50 transactions to a memory task
Use a loop to iterate 50 times and write each transaction to the memory
Ensure each transaction is unique and properly formatted
Verify the transactions after writing them to the memory
Mealy machines have outputs that depend on both present state and input, while Moore machines have outputs that depend only on present state.
Mealy machines have outputs that change asynchronously with input changes
Moore machines have outputs that change synchronously with state changes
Mealy machines have fewer states compared to Moore machines
Example: Traffic light controller is a Mealy machine as the output changes ba...
posted on 24 Jul 2024
randc behavior generates random complex numbers with specified distribution
Use randc to generate random complex numbers
Specify distribution using arguments like mean, variance, etc.
Example: randc(10, 1, 2) generates 10 random complex numbers with mean 1 and variance 2
posted on 23 Nov 2022
Verilog, c++ pointers, mosfets
UART protocol can be used to transmit and receive data between two devices.
UART can be used to communicate between a microcontroller and a computer
UART can be used to send and receive data between two microcontrollers
UART can be used to interface with sensors and actuators
UART can be used to implement a simple command/response protocol
UART can be used to implement a data logging system
UART can be used to receive signals from a microcontroller.
Connect the UART pins of the microcontroller to the UART pins of the receiving device.
Configure the UART settings such as baud rate, parity, and stop bits.
Use a UART library or write code to read the incoming data from the UART buffer.
Process the received data as required by the application.
posted on 10 Dec 2024
I applied via Company Website and was interviewed before Dec 2023. There were 3 interview rounds.
Digital,Verilog, SV based questions with some quants.
SV & UVM concepts with some examples would be fine.
I want to join this organization because of its reputation for innovation and commitment to excellence in design and verification engineering.
I am impressed by the company's track record of developing cutting-edge technologies.
I believe that working at this organization will provide me with opportunities for professional growth and development.
I am excited about the chance to collaborate with a team of talented enginee...
posted on 29 Apr 2024
I applied via campus placement at Indian Institute of Technology (IIT), Kharagpur and was interviewed before Apr 2023. There were 2 interview rounds.
I plan to continue advancing my skills in design verification engineering and eventually move into a leadership role.
Continue taking relevant courses and certifications to stay updated on industry trends
Seek opportunities to lead projects and teams to gain leadership experience
Network with professionals in the field to learn from their experiences and insights
posted on 20 Jun 2022
I applied via LinkedIn and was interviewed before Jun 2021. There were 4 interview rounds.
Medium level
RTL design, test bench , Simulation.
posted on 12 Aug 2024
I applied via campus placement at Birla Institute of Technology and Science (BITS), Pilani and was interviewed in Jul 2024. There was 1 interview round.
To predict if a 32 bit number is divisible by 8, design a circuit using gates.
Use a circuit with AND, OR, and NOT gates to check if the last three bits of the number are all zeros.
If the last three bits are zeros, then the number is divisible by 8.
For example, if the 32 bit number is 11010000, the last three bits are zeros, so it is divisible by 8.
posted on 29 Feb 2024
I applied via Campus Placement and was interviewed in Jan 2024. There was 1 interview round.
posted on 28 Jul 2024
posted on 29 Aug 2024
UVM (Universal Verification Methodology) basic principle is to provide a standardized methodology for verifying digital designs.
UVM is based on SystemVerilog and provides a framework for creating reusable verification environments
It promotes the use of object-oriented programming techniques for creating modular and scalable testbenches
UVM encourages the use of constrained-random stimulus generation and coverage-driven ...
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