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Atria Logic Design & Verification Engineer Interview Questions and Answers

Updated 9 Sep 2024

Atria Logic Design & Verification Engineer Interview Experiences

1 interview found

Interview experience
4
Good
Difficulty level
-
Process Duration
-
Result
-
Round 1 - Technical 

(2 Questions)

  • Q1. Rtl code for fifo
  • Ans. 

    RTL code for FIFO is a hardware description language code that implements a First-In-First-Out buffer.

    • Use Verilog or VHDL to write RTL code for FIFO

    • Define input and output ports for data and control signals

    • Implement logic for enqueue and dequeue operations

    • Use registers or memory elements to store data temporarily

  • Answered by AI
  • Q2. Task to write 50 transactions to a memory
  • Ans. 

    Writing 50 transactions to a memory task

    • Use a loop to iterate 50 times and write each transaction to the memory

    • Ensure each transaction is unique and properly formatted

    • Verify the transactions after writing them to the memory

  • Answered by AI
Round 2 - Technical 

(2 Questions)

  • Q1. Difference between mealy and moore
  • Ans. 

    Mealy machines have outputs that depend on both present state and input, while Moore machines have outputs that depend only on present state.

    • Mealy machines have outputs that change asynchronously with input changes

    • Moore machines have outputs that change synchronously with state changes

    • Mealy machines have fewer states compared to Moore machines

    • Example: Traffic light controller is a Mealy machine as the output changes ba...

  • Answered by AI
  • Q2. Uvm sequencer hand shake

Skills evaluated in this interview

Interview questions from similar companies

Interview experience
3
Average
Difficulty level
-
Process Duration
-
Result
-
Round 1 - Technical 

(5 Questions)

  • Q1. Write code randc behaviour
  • Ans. 

    randc behavior generates random complex numbers with specified distribution

    • Use randc to generate random complex numbers

    • Specify distribution using arguments like mean, variance, etc.

    • Example: randc(10, 1, 2) generates 10 random complex numbers with mean 1 and variance 2

  • Answered by AI
  • Q2. Functinal coverage
  • Q3. Code coverage related questions
  • Q4. Monitor and scoreboard connections
  • Q5. Project related questions

Skills evaluated in this interview

Round 1 - Resume Shortlist 
Pro Tip by AmbitionBox:
Keep your resume crisp and to the point. A recruiter looks at your resume for an average of 6 seconds, make sure to leave the best impression.
View all tips
Round 2 - Aptitude Test 

Verilog, c++ pointers, mosfets

Round 3 - Technical 

(3 Questions)

  • Q1. In depth questions about coding language you chose?
  • Ans. Use pointers to solve a problem
  • Answered Anonymously
  • Q2. Use uart protocol to solve a problem?
  • Ans. 

    UART protocol can be used to transmit and receive data between two devices.

    • UART can be used to communicate between a microcontroller and a computer

    • UART can be used to send and receive data between two microcontrollers

    • UART can be used to interface with sensors and actuators

    • UART can be used to implement a simple command/response protocol

    • UART can be used to implement a data logging system

  • Answered by AI
  • Q3. Use uart to receive signals from micrcontroller
  • Ans. 

    UART can be used to receive signals from a microcontroller.

    • Connect the UART pins of the microcontroller to the UART pins of the receiving device.

    • Configure the UART settings such as baud rate, parity, and stop bits.

    • Use a UART library or write code to read the incoming data from the UART buffer.

    • Process the received data as required by the application.

  • Answered by AI

Interview Preparation Tips

Interview preparation tips for other job seekers - be confident, say i dont know if you really dont know

Skills evaluated in this interview

Interview experience
4
Good
Difficulty level
Moderate
Process Duration
Less than 2 weeks
Result
Selected Selected

I applied via Company Website and was interviewed before Dec 2023. There were 3 interview rounds.

Round 1 - Aptitude Test 

Digital,Verilog, SV based questions with some quants.

Round 2 - Coding Test 

SV & UVM concepts with some examples would be fine.

Round 3 - HR 

(2 Questions)

  • Q1. Self Introduction
  • Q2. Why do you want to join this organisation.
  • Ans. 

    I want to join this organization because of its reputation for innovation and commitment to excellence in design and verification engineering.

    • I am impressed by the company's track record of developing cutting-edge technologies.

    • I believe that working at this organization will provide me with opportunities for professional growth and development.

    • I am excited about the chance to collaborate with a team of talented enginee...

  • Answered by AI
Interview experience
5
Excellent
Difficulty level
Moderate
Process Duration
4-6 weeks
Result
Selected Selected

I applied via campus placement at Indian Institute of Technology (IIT), Kharagpur and was interviewed before Apr 2023. There were 2 interview rounds.

Round 1 - Technical 

(2 Questions)

  • Q1. FSMs, Caches, Mealy, Moore
  • Q2. Caches, verilog, basic coding, d_flip_flop
Round 2 - HR 

(1 Question)

  • Q1. Plans for the future?
  • Ans. 

    I plan to continue advancing my skills in design verification engineering and eventually move into a leadership role.

    • Continue taking relevant courses and certifications to stay updated on industry trends

    • Seek opportunities to lead projects and teams to gain leadership experience

    • Network with professionals in the field to learn from their experiences and insights

  • Answered by AI

I applied via LinkedIn and was interviewed before Jun 2021. There were 4 interview rounds.

Round 1 - Resume Shortlist 
Pro Tip by AmbitionBox:
Don’t add your photo or details such as gender, age, and address in your resume. These details do not add any value.
View all tips
Round 2 - Aptitude Test 

Medium level

Round 3 - Coding Test 

RTL design, test bench , Simulation.

Round 4 - Technical 

(1 Question)

  • Q1. VLSI ic design, CMOS, digital electronics concepts.

Interview Preparation Tips

Interview preparation tips for other job seekers - Particularly for interns, you need to through with concepts related to your experience like hdl languages verilog, sv, scripting language is an added advantage, verification methodology, any projects, AMBA Protocol,Axi....any thing you mentioned in your resume must be Crystal clear..
Interview experience
3
Average
Difficulty level
Moderate
Process Duration
Less than 2 weeks
Result
No response

I applied via campus placement at Birla Institute of Technology and Science (BITS), Pilani and was interviewed in Jul 2024. There was 1 interview round.

Round 1 - Technical 

(2 Questions)

  • Q1. How to predict if a 32 bit number is divisible by 8, draw a circuit using gates
  • Ans. 

    To predict if a 32 bit number is divisible by 8, design a circuit using gates.

    • Use a circuit with AND, OR, and NOT gates to check if the last three bits of the number are all zeros.

    • If the last three bits are zeros, then the number is divisible by 8.

    • For example, if the 32 bit number is 11010000, the last three bits are zeros, so it is divisible by 8.

  • Answered by AI
  • Q2. Various verilog scripting questions

Interview Preparation Tips

Interview preparation tips for other job seekers - Do verilog coding

Skills evaluated in this interview

Interview experience
4
Good
Difficulty level
Moderate
Process Duration
4-6 weeks
Result
No response

I applied via Campus Placement and was interviewed in Jan 2024. There were 2 interview rounds.

Round 1 - Aptitude Test 

Mcq questions based on aptitude(a bit ) and digital design, VLSI, Clock related questions

Round 2 - Technical 

(1 Question)

  • Q1. Had 4 technical interview rounds, Face-to face in Microchip Office 1st round - digital electronics based + coding(verilog or Vhdl) 2nd round - analog, microcontrollers, Digital electronics based questions ...
Interview experience
5
Excellent
Difficulty level
-
Process Duration
-
Result
-
Round 1 - One-on-one 

(2 Questions)

  • Q1. Project questions
  • Q2. Sv and uvm basics
Round 2 - One-on-one 

(2 Questions)

  • Q1. Pcie basic questions
  • Q2. SV and UVM basics
Interview experience
5
Excellent
Difficulty level
-
Process Duration
-
Result
-
Round 1 - One-on-one 

(2 Questions)

  • Q1. Assertions and coverage
  • Q2. Umv basic principle
  • Ans. 

    UVM (Universal Verification Methodology) basic principle is to provide a standardized methodology for verifying digital designs.

    • UVM is based on SystemVerilog and provides a framework for creating reusable verification environments

    • It promotes the use of object-oriented programming techniques for creating modular and scalable testbenches

    • UVM encourages the use of constrained-random stimulus generation and coverage-driven ...

  • Answered by AI

Interview Preparation Tips

Interview preparation tips for other job seekers - Prepare basics

Atria Logic Interview FAQs

How many rounds are there in Atria Logic Design & Verification Engineer interview?
Atria Logic interview process usually has 2 rounds. The most common rounds in the Atria Logic interview process are Technical.
How to prepare for Atria Logic Design & Verification Engineer interview?
Go through your CV in detail and study all the technologies mentioned in your CV. Prepare at least two technologies or languages in depth if you are appearing for a technical interview at Atria Logic. The most common topics and skills that interviewers at Atria Logic expect are Debugging, FPGA, Perl, System Verilog and VHDL.
What are the top questions asked in Atria Logic Design & Verification Engineer interview?

Some of the top questions asked at the Atria Logic Design & Verification Engineer interview -

  1. Task to write 50 transactions to a mem...read more
  2. Difference between mealy and mo...read more
  3. Rtl code for f...read more

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Atria Logic Design & Verification Engineer Salary
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₹2.4 L/yr - ₹8 L/yr
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