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Atria Logic Asic Design Verification Engineer Interview Questions and Answers

Updated 12 Jun 2024

Atria Logic Asic Design Verification Engineer Interview Experiences

1 interview found

Interview experience
1
Bad
Difficulty level
-
Process Duration
-
Result
-
Round 1 - One-on-one 

(1 Question)

  • Q1. Write a 8X1 mux using if else with clock and reset
  • Ans. 

    Implementing an 8X1 mux using if else statements with clock and reset

    • Declare input signals, output signal, clock and reset signals

    • Use if else statements to select the output based on the select lines

    • Ensure proper handling of clock and reset signals

    • Example: if(sel == 3) output = in3;

  • Answered by AI

Interview Preparation Tips

Interview preparation tips for other job seekers - I made a blunder mistake in answering the question

Interview questions from similar companies

Interview experience
3
Average
Difficulty level
Moderate
Process Duration
Less than 2 weeks
Result
No response

I applied via campus placement at Birla Institute of Technology and Science (BITS), Pilani and was interviewed in Jul 2024. There was 1 interview round.

Round 1 - Technical 

(2 Questions)

  • Q1. How to predict if a 32 bit number is divisible by 8, draw a circuit using gates
  • Ans. 

    To predict if a 32 bit number is divisible by 8, design a circuit using gates.

    • Use a circuit with AND, OR, and NOT gates to check if the last three bits of the number are all zeros.

    • If the last three bits are zeros, then the number is divisible by 8.

    • For example, if the 32 bit number is 11010000, the last three bits are zeros, so it is divisible by 8.

  • Answered by AI
  • Q2. Various verilog scripting questions

Interview Preparation Tips

Interview preparation tips for other job seekers - Do verilog coding

Skills evaluated in this interview

Interview experience
4
Good
Difficulty level
Hard
Process Duration
Less than 2 weeks
Result
Selected Selected

I applied via campus placement at Indian Institute of Technology (IIT), Kanpur and was interviewed before Mar 2023. There was 1 interview round.

Round 1 - Technical 

(5 Questions)

  • Q1. Design of mux and ff
  • Ans. 

    A multiplexer (mux) is a digital circuit that selects one of several input signals and forwards it to a single output. A flip-flop (ff) is a type of latch circuit that stores a single bit of data.

    • Mux design involves selecting one of multiple input signals based on a control signal

    • FF design involves storing a single bit of data using a clock signal

    • Mux can be implemented using logic gates like AND, OR, and NOT gates

    • FF ca...

  • Answered by AI
  • Q2. Basics of sv n verilog
  • Q3. Sta question about timing violation
  • Q4. Thesis related question
  • Q5. Some basic design question

Interview Preparation Tips

Interview preparation tips for other job seekers - good at basics of sta, sv and uvm
Interview experience
3
Average
Difficulty level
-
Process Duration
-
Result
-
Round 1 - Technical 

(5 Questions)

  • Q1. Write code randc behaviour
  • Ans. 

    randc behavior generates random complex numbers with specified distribution

    • Use randc to generate random complex numbers

    • Specify distribution using arguments like mean, variance, etc.

    • Example: randc(10, 1, 2) generates 10 random complex numbers with mean 1 and variance 2

  • Answered by AI
  • Q2. Functinal coverage
  • Q3. Code coverage related questions
  • Q4. Monitor and scoreboard connections
  • Q5. Project related questions

Skills evaluated in this interview

Interview experience
5
Excellent
Difficulty level
-
Process Duration
-
Result
-
Round 1 - Technical 

(2 Questions)

  • Q1. What is cross talk
  • Ans. 

    Cross talk is the unwanted transfer of signals between different components or traces on a circuit board.

    • Occurs when signals from one trace interfere with signals on another trace

    • Can lead to signal distortion or errors in data transmission

    • Prevented by proper spacing and shielding between traces

    • Example: Cross talk between data lines on a PCB causing errors in communication

  • Answered by AI
  • Q2. How to define generated clocks through edges
  • Ans. 

    Generated clocks through edges are defined by specifying the source clock and the edge on which the generated clock is based.

    • Specify the source clock for the generated clock

    • Define the edge (rising/falling) on which the generated clock is based

    • Use tools like Synopsys Design Compiler to define generated clocks

  • Answered by AI
Interview experience
5
Excellent
Difficulty level
-
Process Duration
-
Result
-
Round 1 - One-on-one 

(2 Questions)

  • Q1. Assertions and coverage
  • Q2. Umv basic principle
  • Ans. 

    UVM (Universal Verification Methodology) basic principle is to provide a standardized methodology for verifying digital designs.

    • UVM is based on SystemVerilog and provides a framework for creating reusable verification environments

    • It promotes the use of object-oriented programming techniques for creating modular and scalable testbenches

    • UVM encourages the use of constrained-random stimulus generation and coverage-driven ...

  • Answered by AI

Interview Preparation Tips

Interview preparation tips for other job seekers - Prepare basics
Interview experience
3
Average
Difficulty level
Moderate
Process Duration
2-4 weeks
Result
Not Selected

I applied via Campus Placement and was interviewed in Jan 2024. There was 1 interview round.

Round 1 - Technical 

(2 Questions)

  • Q1. Basics of analog , digital and vlsi
  • Q2. On face to face interview, they asked me abt my projects , digital, little analog , vlsi ( verilog), microcontrollers and c programming

Interview Preparation Tips

Interview preparation tips for other job seekers - Prepare well on your basics
Interview experience
5
Excellent
Difficulty level
-
Process Duration
-
Result
-
Round 1 - One-on-one 

(1 Question)

  • Q1. Is setup and hold uncertainty values are different
  • Ans. 

    Yes, setup and hold uncertainty values are different in physical design engineering.

    • Setup uncertainty is related to the arrival time of the data signal at the input of the flip-flop, while hold uncertainty is related to the removal time of the data signal.

    • Setup time is the minimum amount of time the data input must be stable before the clock edge, while hold time is the minimum amount of time the data input must be sta...

  • Answered by AI
Interview experience
3
Average
Difficulty level
Moderate
Process Duration
Less than 2 weeks
Result
No response

I applied via campus placement at Birla Institute of Technology and Science (BITS), Pilani and was interviewed in Jul 2024. There was 1 interview round.

Round 1 - Technical 

(2 Questions)

  • Q1. How to predict if a 32 bit number is divisible by 8, draw a circuit using gates
  • Ans. 

    To predict if a 32 bit number is divisible by 8, design a circuit using gates.

    • Use a circuit with AND, OR, and NOT gates to check if the last three bits of the number are all zeros.

    • If the last three bits are zeros, then the number is divisible by 8.

    • For example, if the 32 bit number is 11010000, the last three bits are zeros, so it is divisible by 8.

  • Answered by AI
  • Q2. Various verilog scripting questions

Interview Preparation Tips

Interview preparation tips for other job seekers - Do verilog coding

Skills evaluated in this interview

Interview experience
4
Good
Difficulty level
Moderate
Process Duration
Less than 2 weeks
Result
Not Selected

I applied via LinkedIn and was interviewed in Oct 2023. There were 2 interview rounds.

Round 1 - Aptitude Test 

40 aptitude qns and some mcqs on basic programming

Round 2 - Technical 

(4 Questions)

  • Q1. I was asked to write two sum, palindrome function and merge sort code in whatever language I'm comfortable in
  • Q2. Two sum- return true or false
  • Ans. 

    Given an array of integers, determine if there are two numbers that add up to a specific target.

    • Iterate through the array and store each element in a hash set.

    • For each element, check if the difference between the target and the element exists in the hash set.

    • If the difference exists, return true; otherwise, continue iterating.

    • Example: nums = [2, 7, 11, 15], target = 9. The function should return true as 2 + 7 = 9.

  • Answered by AI
  • Q3. Merge sort function code
  • Q4. Palindromic string or not

Skills evaluated in this interview

Atria Logic Interview FAQs

How many rounds are there in Atria Logic Asic Design Verification Engineer interview?
Atria Logic interview process usually has 1 rounds. The most common rounds in the Atria Logic interview process are One-on-one Round.

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