Atria Logic Asic Design Verification Engineer Interview Questions and Answers

Q1. Design of mux and ff
Ans. 
A multiplexer (mux) is a digital circuit that selects one of several input signals and forwards it to a single output. A flip-flop (ff) is a type of latch circuit that stores a single bit of data.
• Mux design involves selecting one of multiple input signals based on a control signal

• FF design involves storing a single bit of data using a clock signal

• Mux can be implemented using logic gates like AND, OR, and NOT gates

• FF ca...read more
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Q2. Basics of sv n verilog
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Q3. Sta question about timing violation
Ans. 
Timing violations occur when a signal does not meet the required timing constraints in digital circuits.
• Timing violations can lead to incorrect circuit behavior or functional failures.

• Common types include setup time violations and hold time violations.

• Example: A setup time violation occurs if data arrives too late before the clock edge.

• Hold time violations happen when data changes too soon after the clock edge.

• Static T...read more
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Q4. Thesis related question
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Q5. Some basic design question
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Q1. Asked the working experience and the related skills to the new job
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Q1. Coding questions in Verilog, Systemverilog, random constraints such as how to write a onehot in different ways
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Q1. Asked the expectation of the base salary and overall compensation
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Q1. Assertions and coverage
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Q2. Umv basic principle
Ans. 
UVM (Universal Verification Methodology) basic principle is to provide a standardized methodology for verifying digital designs.
• UVM is based on SystemVerilog and provides a framework for creating reusable verification environments

• It promotes the use of object-oriented programming techniques for creating modular and scalable testbenches

• UVM encourages the use of constrained-random stimulus generation and coverage-driven ...read more
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Q1. The question was draw cmos inverter transfer characteristics and by varying some parameters they asked their effects on it.
Ans. 
CMOS inverter transfer characteristics illustrate the relationship between input and output voltages, affected by various parameters.
• Vth (threshold voltage) affects the switching point; higher Vth shifts the curve right.

• W/L ratio (width-to-length) influences drive strength; larger W/L increases output current.

• Supply voltage (Vdd) impacts the output swing; higher Vdd results in a larger output voltage range.

• Temperature ...read more
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Q1. Questions were on cashe memory, simple programming questions, puzzles
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Round duration - 120 Minutes
Round difficulty - Medium

Round duration - 60 Minutes
Round difficulty - Easy

Q1. 
Insertion Sort in a Linked List
Given a singly linked list with 'N' nodes containing integer values, your task is to sort the list using insertion sort and output the sorted list.
Insertion Sort is an al...read more
Ans. 
Implement insertion sort algorithm on a singly linked list with integer values.
• Traverse the linked list and for each node, find its correct position in the sorted list.

• Remove the node from the original list and insert it at the correct position in the sorted list.

• Repeat this process until all nodes are sorted.

• Ensure the implementation is in-place, without using extra space.

• Handle edge cases like empty list or single no...read more
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Q2. 
Implement Stack with Linked List
Your task is to implement a Stack data structure using a Singly Linked List.
Explanation:
Create a class named Stack which supports the following operations, each in O(1...read more
Ans. 
Implement a Stack data structure using a Singly Linked List with operations in O(1) time.
• Create a class named Stack with getSize, isEmpty, push, pop, and getTop methods.

• Use a Singly Linked List to store the elements of the stack.

• Ensure each operation runs in O(1) time complexity.

• Handle cases where the stack is empty appropriately.

• Implement the logic for each query type as specified in the input and output sections.
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Q3. 
Prime Numbers within a Range
Given an integer N, determine and print all the prime numbers between 2 and N, inclusive.
Input:
Integer N
Output:
Prime numbers printed on separate lines
Example:
Input...read more
Ans. 
Generate and print all prime numbers between 2 and N, inclusive.
• Iterate from 2 to N and check if each number is prime

• Use a helper function to determine if a number is prime

• Print each prime number on a new line
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Round duration - 45 Minutes
Round difficulty - Medium

This round was based on oops concepts and their applications and about STLs.

Q1. 
Rectangular Numbers Pattern
Given a number N, generate a pattern where the outer rectangle is filled with the number N, and the inner rectangles contain decreasing numbers down to 1.
Input:
The input be...read more
Ans. 
Generate a rectangular pattern with outer rectangle filled with N and inner rectangles containing decreasing numbers.
• Create a 2-D array with dimensions based on input N

• Fill the outer rectangle with N and inner rectangles with decreasing numbers down to 1

• Adjust the values in the inner rectangles based on the layer number

• Return the generated pattern as a 2-D list/array
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Round duration - 30 Minutes
Round difficulty - Easy

This around was basically to judge my communication and behavioral skills.