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Implementing an 8X1 mux using if else statements with clock and reset
Declare input signals, output signal, clock and reset signals
Use if else statements to select the output based on the select lines
Ensure proper handling of clock and reset signals
Example: if(sel == 3) output = in3;
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posted on 12 Aug 2024
I applied via Campus Placement and was interviewed in Jul 2024. There was 1 interview round.
To predict if a 32 bit number is divisible by 8, design a circuit using gates.
Use a circuit with AND, OR, and NOT gates to check if the last three bits of the number are all zeros.
If the last three bits are zeros, then the number is divisible by 8.
For example, if the 32 bit number is 11010000, the last three bits are zeros, so it is divisible by 8.
posted on 18 Mar 2024
I applied via Campus Placement and was interviewed before Mar 2023. There was 1 interview round.
A multiplexer (mux) is a digital circuit that selects one of several input signals and forwards it to a single output. A flip-flop (ff) is a type of latch circuit that stores a single bit of data.
Mux design involves selecting one of multiple input signals based on a control signal
FF design involves storing a single bit of data using a clock signal
Mux can be implemented using logic gates like AND, OR, and NOT gates
FF ca...
Timing violations occur when a signal does not meet the required timing constraints in digital circuits.
Timing violations can lead to incorrect circuit behavior or functional failures.
Common types include setup time violations and hold time violations.
Example: A setup time violation occurs if data arrives too late before the clock edge.
Hold time violations happen when data changes too soon after the clock edge.
Static T...
posted on 25 Jun 2021
I applied via Referral and was interviewed before Jun 2020. There was 1 interview round.
posted on 29 Aug 2024
UVM (Universal Verification Methodology) basic principle is to provide a standardized methodology for verifying digital designs.
UVM is based on SystemVerilog and provides a framework for creating reusable verification environments
It promotes the use of object-oriented programming techniques for creating modular and scalable testbenches
UVM encourages the use of constrained-random stimulus generation and coverage-driven ...
posted on 15 Apr 2024
I applied via Referral and was interviewed before Apr 2023. There were 3 interview rounds.
posted on 5 Apr 2024
CMOS inverter transfer characteristics illustrate the relationship between input and output voltages, affected by various parameters.
Vth (threshold voltage) affects the switching point; higher Vth shifts the curve right.
W/L ratio (width-to-length) influences drive strength; larger W/L increases output current.
Supply voltage (Vdd) impacts the output swing; higher Vdd results in a larger output voltage range.
Temperature ...
I applied via Referral and was interviewed in Aug 2021. There was 1 interview round.
I applied via Recruitment Consultant and was interviewed before May 2020. There were 3 interview rounds.
Clone a linked list with random pointers.
Create a new node for each node in the original list.
Store the mapping between the original and cloned nodes in a hash table.
Traverse the original list again and set the random pointers in the cloned list using the hash table.
Return the head of the cloned list.
I appeared for an interview in Aug 2017.
based on 1 interview experience
Verification Engineer
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