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Atria Logic Asic Design Verification Engineer Interview Questions and Answers

Updated 12 Jun 2024

Atria Logic Asic Design Verification Engineer Interview Experiences

1 interview found

Interview experience
1
Bad
Difficulty level
-
Process Duration
-
Result
-
Round 1 - One-on-one 

(1 Question)

  • Q1. Write a 8X1 mux using if else with clock and reset
  • Ans. 

    Implementing an 8X1 mux using if else statements with clock and reset

    • Declare input signals, output signal, clock and reset signals

    • Use if else statements to select the output based on the select lines

    • Ensure proper handling of clock and reset signals

    • Example: if(sel == 3) output = in3;

  • Answered by AI

Interview Preparation Tips

Interview preparation tips for other job seekers - I made a blunder mistake in answering the question

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2w
toobluntforu
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works at
Cvent
Can speak English, can’t deliver in interviews
I feel like I can't speak fluently during interviews. I do know english well and use it daily to communicate, but the moment I'm in an interview, I just get stuck. since it's not my first language, I struggle to express what I actually feel. I know the answer in my head, but I just can’t deliver it properly at that moment. Please guide me
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Interview experience
3
Average
Difficulty level
Moderate
Process Duration
Less than 2 weeks
Result
No response

I applied via Campus Placement and was interviewed in Jul 2024. There was 1 interview round.

Round 1 - Technical 

(2 Questions)

  • Q1. How to predict if a 32 bit number is divisible by 8, draw a circuit using gates
  • Ans. 

    To predict if a 32 bit number is divisible by 8, design a circuit using gates.

    • Use a circuit with AND, OR, and NOT gates to check if the last three bits of the number are all zeros.

    • If the last three bits are zeros, then the number is divisible by 8.

    • For example, if the 32 bit number is 11010000, the last three bits are zeros, so it is divisible by 8.

  • Answered by AI
  • Q2. Various verilog scripting questions

Interview Preparation Tips

Interview preparation tips for other job seekers - Do verilog coding

Skills evaluated in this interview

Asic Design Verification Engineer Interview Questions Asked at Other Companies

asked in Synopsys
Q1. Write Verilog code to divide the frequency of a 100Hz square wave ... read more
Q2. How can you predict if a 32-bit number is divisible by 8? Draw a ... read more
Q3. Conversation one number system to other. Make nand gate using Mux ... read more
Q4. What is a bus functional model and how is it written?
asked in Synopsys
Q5. Why do you want to work at Synopsys?
Interview experience
4
Good
Difficulty level
Hard
Process Duration
Less than 2 weeks
Result
Selected Selected

I applied via Campus Placement and was interviewed before Mar 2023. There was 1 interview round.

Round 1 - Technical 

(5 Questions)

  • Q1. Design of mux and ff
  • Ans. 

    A multiplexer (mux) is a digital circuit that selects one of several input signals and forwards it to a single output. A flip-flop (ff) is a type of latch circuit that stores a single bit of data.

    • Mux design involves selecting one of multiple input signals based on a control signal

    • FF design involves storing a single bit of data using a clock signal

    • Mux can be implemented using logic gates like AND, OR, and NOT gates

    • FF ca...

  • Answered by AI
  • Q2. Basics of sv n verilog
  • Q3. Sta question about timing violation
  • Ans. 

    Timing violations occur when a signal does not meet the required timing constraints in digital circuits.

    • Timing violations can lead to incorrect circuit behavior or functional failures.

    • Common types include setup time violations and hold time violations.

    • Example: A setup time violation occurs if data arrives too late before the clock edge.

    • Hold time violations happen when data changes too soon after the clock edge.

    • Static T...

  • Answered by AI
  • Q4. Thesis related question
  • Q5. Some basic design question

Interview Preparation Tips

Interview preparation tips for other job seekers - good at basics of sta, sv and uvm

I applied via Referral and was interviewed before Jun 2020. There was 1 interview round.

Interview Questionnaire 

1 Question

  • Q1. Basic questions, project experience, scenario based questions

Interview Preparation Tips

Interview preparation tips for other job seekers - Be prepared on basics and projects
Interview experience
5
Excellent
Difficulty level
-
Process Duration
-
Result
-
Round 1 - One-on-one 

(2 Questions)

  • Q1. Assertions and coverage
  • Q2. Umv basic principle
  • Ans. 

    UVM (Universal Verification Methodology) basic principle is to provide a standardized methodology for verifying digital designs.

    • UVM is based on SystemVerilog and provides a framework for creating reusable verification environments

    • It promotes the use of object-oriented programming techniques for creating modular and scalable testbenches

    • UVM encourages the use of constrained-random stimulus generation and coverage-driven ...

  • Answered by AI

Interview Preparation Tips

Interview preparation tips for other job seekers - Prepare basics
Interview experience
5
Excellent
Difficulty level
Moderate
Process Duration
4-6 weeks
Result
Selected Selected

I applied via Referral and was interviewed before Apr 2023. There were 3 interview rounds.

Round 1 - One-on-one 

(1 Question)

  • Q1. Asked the working experience and the related skills to the new job
Round 2 - Technical 

(1 Question)

  • Q1. Coding questions in Verilog, Systemverilog, random constraints such as how to write a onehot in different ways
Round 3 - HR 

(1 Question)

  • Q1. Asked the expectation of the base salary and overall compensation

Interview Preparation Tips

Topics to prepare for Micron Technology Verification Engineer interview:
  • SystemVerilog coding
Interview experience
4
Good
Difficulty level
-
Process Duration
-
Result
-
Round 1 - Technical 

(1 Question)

  • Q1. The question was draw cmos inverter transfer characteristics and by varying some parameters they asked their effects on it.
  • Ans. 

    CMOS inverter transfer characteristics illustrate the relationship between input and output voltages, affected by various parameters.

    • Vth (threshold voltage) affects the switching point; higher Vth shifts the curve right.

    • W/L ratio (width-to-length) influences drive strength; larger W/L increases output current.

    • Supply voltage (Vdd) impacts the output swing; higher Vdd results in a larger output voltage range.

    • Temperature ...

  • Answered by AI
Are these interview questions helpful?

I applied via Referral and was interviewed in Aug 2021. There was 1 interview round.

Round 1 - Technical 

(1 Question)

  • Q1. Questions were on cashe memory, simple programming questions, puzzles

Interview Preparation Tips

Interview preparation tips for other job seekers - Prepare for computer architecture

I applied via Recruitment Consultant and was interviewed before May 2020. There were 3 interview rounds.

Interview Questionnaire 

2 Questions

  • Q1. DS and Algo questions based on DP and backtracking
  • Q2. Clone linked list with random pointers.
  • Ans. 

    Clone a linked list with random pointers.

    • Create a new node for each node in the original list.

    • Store the mapping between the original and cloned nodes in a hash table.

    • Traverse the original list again and set the random pointers in the cloned list using the hash table.

    • Return the head of the cloned list.

  • Answered by AI

Interview Preparation Tips

Interview preparation tips for other job seekers - Mostly DS and Algo rounds followed by design rounds. Sometimes there can be language specific questions.

Skills evaluated in this interview

I appeared for an interview in Aug 2017.

Interview Preparation Tips

Round: Test
Duration: 1 hour 30 minutes
Total Questions: 60

Round: Technical Interview
Experience: Questions about DS , CN and basic resume

Round: Technical Interview
Experience: Questions about RT OS and memory mapping. And other operating system related questions.
Projects done so far.

Atria Logic Interview FAQs

How many rounds are there in Atria Logic Asic Design Verification Engineer interview?
Atria Logic interview process usually has 1 rounds. The most common rounds in the Atria Logic interview process are One-on-one Round.

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Overall Interview Experience Rating

1/5

based on 1 interview experience

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