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I applied via Company Website and was interviewed in Jan 2024. There were 3 interview rounds.
You have to cut a cake maximum 3 times which should make 8 equal halves
An XOR gate can be designed using a 2:1 MUX by connecting the inputs to the select lines and the outputs to the data inputs.
Connect one input of the XOR gate to the select line of the MUX
Connect the other input of the XOR gate to the inverted select line of the MUX
Connect the outputs of the MUX to the XOR gate's output
An AND gate can be designed using a 2:1 multiplexer by connecting one input to select line and the other input to the data input.
Connect one input of the AND gate to the select line of the 2:1 mux
Connect the other input of the AND gate to the data input of the 2:1 mux
The output of the 2:1 mux will be the output of the AND gate
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posted on 31 Dec 2024
I was interviewed in Dec 2024.
posted on 2 Oct 2024
I applied via campus placement at Netaji Subhas Institute of Technology (NSIT) and was interviewed in Sep 2024. There were 2 interview rounds.
Basic aptitude-10 question,digital moderate -Question,analog moderate -10 question,verilog and system verilog -10 question
posted on 24 Jul 2024
randc behavior generates random complex numbers with specified distribution
Use randc to generate random complex numbers
Specify distribution using arguments like mean, variance, etc.
Example: randc(10, 1, 2) generates 10 random complex numbers with mean 1 and variance 2
posted on 7 May 2024
I applied via Referral and was interviewed in Apr 2024. There was 1 interview round.
Coverage-driven verification techniques are used to ensure all possible state transitions are exercised.
Coverage metrics like state, transition, and toggle coverage can be used to track the completeness of state transitions.
Writing directed tests to cover specific state transitions can help achieve higher coverage.
Random stimulus generation can also be used to explore different state transitions.
Functional coverage can...
posted on 6 Mar 2024
I was interviewed in Feb 2024.
I have done internship in Moschip Institute of Silicon Systems.
m_sequencer and p_sequencer are components used in design and verification for sequencing operations.
m_sequencer and p_sequencer are commonly used in digital design for controlling the sequence of operations.
m_sequencer typically refers to a master sequencer, while p_sequencer refers to a peripheral sequencer.
These components are often used in verification environments to ensure proper sequencing of events.
For example,...
Factory override in UVM allows users to replace default factory methods with custom implementations.
Factory override is used to customize the behavior of UVM components without modifying the original source code.
It allows users to replace default factory methods with custom implementations to meet specific requirements.
Factory override can be useful for debugging, testing, or adding new features to existing UVM compone...
A call back in UVM is a mechanism used to notify a component about a specific event or condition.
A call back is defined using a function or task in the UVM component.
It is registered with the UVM framework to be executed when a certain event occurs.
Call backs are commonly used for handling events like transaction completion or error detection.
posted on 20 Jun 2022
I applied via LinkedIn and was interviewed before Jun 2021. There were 4 interview rounds.
Medium level
RTL design, test bench , Simulation.
posted on 16 Aug 2023
I applied via Naukri.com and was interviewed in Jul 2023. There were 2 interview rounds.
posted on 27 Sep 2022
I applied via Company Website and was interviewed in Mar 2022. There were 3 interview rounds.
Had basic aptitude questions, verilog , c programming, digital electronics, analog electronics,computer architecture.
posted on 28 Jul 2024
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