Senior Engineer, Design Verification Engineering

The SVV team is looking for a self-motivated individual with proven experience in analog behavioral modeling and mixed-signal design verification, along with strong analog design fundamentals to contribute to the Mixed-Signal DV domain. This role will give this individual an opportunity to work with BUs spanning ADIs breadth of industry-leading mixed-signal product portfolio and make significant impact.

Job Responsibilities:

• Develop, deploy, and support Design Verification methodologies with a special focus on Analog/Mixed-Signal and Low-Power
• Champion state-of-the-art circuit simulation and behavioral modeling tools and techniques, and apply to complex A/MS SoC designs with an emphasis on low-power
• Provide high quality proactive application engineering support for both in-house and commercial EDA tools and flows
• Assess, implement, and coordinate the development of new capabilities in the A/MS Design Verification and ensure the success of IC design teams.

Position Requirements

• B. Tech. required, M. Tech. preferred with strong fundamentals in IC circuit design of ADCs, DACs, RF Transceivers, Voltage Regulators etc.
• Proven skills in analog IC design and behavioral modeling are required.
• Proficiency with EDA tools and Design Verification methodologies for low-power, mixed-signal ICs including schematic capture, layout, simulation, familiarity with low-power intent (CPF/UPF/IEEE-1801) and A/MS behavioral modeling is highly desirable.
• Exposure to CAD tool development, experience in software programming (C++, Perl, Python) and behavioral modeling (SystemVerilog RNM, Verilog-AMS, Verilog-A) is a plus.
• Should be able to communicate technical details very effectively with both customers (circuit designers) and peers.