Analog Devices Design & Verification Engineer Interview Questions and Answers

Basic aptitude-10 question,digital moderate -Question,analog moderate -10 question,verilog and system verilog -10 question

Q1. Latches and flip flop all characteristics equation and proof of the characteristics equation in flip flop.applications of flip flop
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Q2. OOPS,INHERITANCE,VERILOG,BLOCKING - NON BLOCKING ASSIGNMENT OPERATOR and all the basic operations of verilog .
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Q3. Discussion on work experience.
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Q1. Simple FSM given similar to mux and asked for testcases and assertions.
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Q2. Coverage to write transitions of states.
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Coverage-driven verification techniques are used to ensure all possible state transitions are exercised.
• Coverage metrics like state, transition, and toggle coverage can be used to track the completeness of state transitions.

• Writing directed tests to cover specific state transitions can help achieve higher coverage.

• Random stimulus generation can also be used to explore different state transitions.

• Functional coverage can...read more
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I have done internship in Moschip Institute of Silicon Systems.

Q1. Basic questions on Digital Electronics, Verilog, System Verilog and UVM.
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Q2. What is m_sequencer and p_sequencer?
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m_sequencer and p_sequencer are components used in design and verification for sequencing operations.
• m_sequencer and p_sequencer are commonly used in digital design for controlling the sequence of operations.

• m_sequencer typically refers to a master sequencer, while p_sequencer refers to a peripheral sequencer.

• These components are often used in verification environments to ensure proper sequencing of events.

• For example,...read more
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Q3. What is factory override in UVM?
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Factory override in UVM allows users to replace default factory methods with custom implementations.
• Factory override is used to customize the behavior of UVM components without modifying the original source code.

• It allows users to replace default factory methods with custom implementations to meet specific requirements.

• Factory override can be useful for debugging, testing, or adding new features to existing UVM compone...read more
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Q4. What is the call back in UVM?
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A call back in UVM is a mechanism used to notify a component about a specific event or condition.
• A call back is defined using a function or task in the UVM component.

• It is registered with the UVM framework to be executed when a certain event occurs.

• Call backs are commonly used for handling events like transaction completion or error detection.
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Q5. Questions relatedto ethernet project?
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Medium level

RTL design, test bench , Simulation.

Q1. VLSI ic design, CMOS, digital electronics concepts.
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Q1. SV, UVM, and interview questions related to AMBA protocol.
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Q2. Logical questions based on constraint
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Q3. Question based on SV oops
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Q4. Question based on UVM tb
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Q5. Question bases on assertions and coverage
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Had basic aptitude questions, verilog , c programming, digital electronics, analog electronics,computer architecture.

Q1. Basic questions related to electronics
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Q2. Question related to aptitude
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Q1. Project questions
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Q2. Sv and uvm basics
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Q1. Pcie basic questions
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Q2. SV and UVM basics
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