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I applied via Campus Placement and was interviewed in Jan 2016. There were 3 interview rounds.
Reduction of 3D Kmap involves simplifying a 3D truth table to minimize the number of logic gates required.
3D Kmap is a graphical representation of a truth table with three variables
Reduction involves grouping adjacent cells with the same output value
The goal is to minimize the number of groups and variables in each group
Simplification can be done using Boolean algebra or Karnaugh maps
Example: Reducing a 3D Kmap with in
A design engineer is responsible for creating and developing innovative designs for products or systems.
Designing and prototyping new products
Collaborating with cross-functional teams to ensure design feasibility
Using CAD software to create detailed drawings and specifications
Testing and evaluating prototypes to ensure functionality and performance
Making design improvements based on feedback and testing results
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posted on 28 Aug 2016
I applied via Campus Placement
posted on 28 May 2024
I applied via Campus Placement and was interviewed in Nov 2023. There were 2 interview rounds.
posted on 10 Jul 2024
I applied via Job Portal and was interviewed in Jan 2024. There was 1 interview round.
A C program to generate Fibonacci series
Declare variables to store current and previous Fibonacci numbers
Use a loop to calculate and print Fibonacci numbers
Handle edge cases like 0 and 1 separately
A up counter circuit is a digital circuit that counts upwards in binary sequence.
Use flip-flops to store the count value
Connect the output of one flip-flop to the clock input of the next flip-flop
Use logic gates to control the counting sequence
Add a reset input to clear the count when needed
IV characteristics of CMOS inverter show the relationship between input voltage and output current.
CMOS inverter has two transistors - NMOS and PMOS connected in series.
For low input voltage, NMOS is ON and PMOS is OFF, resulting in low output voltage.
For high input voltage, NMOS is OFF and PMOS is ON, resulting in high output voltage.
The transition between low and high output voltage occurs at the threshold voltage.
Th...
Set up time and hold time are timing requirements in digital circuits to ensure proper operation.
Set up time is the minimum time before the clock edge that the input signal must be stable.
Hold time is the minimum time after the clock edge that the input signal must be maintained stable.
Violating set up time can lead to incorrect data being latched.
Violating hold time can lead to metastability issues.
Examples: In a flip...
C, c++ python and simple aptitude
A CMOS inverter is a type of digital logic gate that switches between high and low voltage levels.
CMOS stands for Complementary Metal-Oxide-Semiconductor
It consists of a PMOS (p-type metal-oxide-semiconductor) and NMOS (n-type metal-oxide-semiconductor) transistor connected in series
When the input is high, the PMOS transistor conducts and the output is low
When the input is low, the NMOS transistor conducts and the outp...
I applied via Walk-in and was interviewed in Feb 2024. There were 3 interview rounds.
Basic aptitude questions
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