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I have worked on various digital projects including designing and implementing digital circuits, developing microcontroller-based systems, and creating digital signal processing algorithms.
Designed and implemented digital circuits using Verilog and VHDL
Developed microcontroller-based systems using Arduino and Raspberry Pi
Created digital signal processing algorithms using MATLAB and Python
Worked on FPGA-based projects s...
Step responses for RC circuits with increasing complexity can be plotted.
Step response of a simple RC circuit with one resistor and one capacitor can be plotted.
Adding more resistors and capacitors in series or parallel can increase the complexity of the circuit.
Different values of resistors and capacitors can also affect the step response.
Simulation software like LTSpice can be used to plot step responses.
Step respons...
To determine the sign on the opamp and output impedances of transistor circuits without pen and paper.
Use mental math to determine the sign on the opamp based on the input and feedback signals
Estimate the output impedance by considering the transistor's characteristics and circuit topology
Practice mental math and circuit analysis to improve speed and accuracy
Use simulation software to verify calculations and gain addit
The minimum sampling frequency required for a passband signal from 5kHz to 10 kHz is 20 kHz.
The Nyquist-Shannon sampling theorem states that the minimum sampling frequency should be twice the highest frequency component of the signal.
In this case, the highest frequency component is 10 kHz, so the minimum sampling frequency required is 20 kHz.
Sampling at a lower frequency can result in aliasing, where higher frequency c...
State diagrams are visual representations of the states and transitions of a system.
Identify the states of the system
Determine the events that trigger state transitions
Draw the state diagram using appropriate symbols and notation
Label the states and transitions
Include any necessary conditions or actions for each transition
DDP stands for Design Data Package, which is a collection of documents and files that define a product's design.
DDP includes design specifications, drawings, schematics, and other relevant documents.
It is used to communicate the design intent to manufacturers and suppliers.
DDP ensures that the product is manufactured according to the design specifications.
It also helps in maintaining the product's quality and consisten...
Draw log(Id) vs Vgs for a MOSFET and explain the curve. Questions on subthreshold slope, howVth varies with length, asked to explain what is DIBL
The curve shows the relationship between drain current and gate-source voltage
Subthreshold slope is the rate of change of drain current with respect to gate voltage
Vth varies with length due to the effect of channel length modulation
DIBL stands for Drain Induced Barrier Loweri...
The design flow involves several stages from logic design to post silicon validation.
Logic design using hardware description languages (HDL)
Functional verification using simulation and emulation
Synthesis and optimization of design for target technology
Physical design including floor planning, placement, and routing
Design for testability (DFT) insertion
Manufacturing and fabrication of the design
Post silicon validation a
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posted on 1 Dec 2024
I applied via campus placement at Indian School of Mines (ISM), Dhanbad and was interviewed in Nov 2024. There was 1 interview round.
NAND gate can be implemented using a 2:1 multiplexer by connecting one input to select line and the other input to one of the data inputs.
Connect one input of the NAND gate to the select line of the 2:1 mux.
Connect the other input of the NAND gate to one of the data inputs of the 2:1 mux.
Connect the other data input of the 2:1 mux to ground.
The output of the 2:1 mux will be the output of the NAND gate.
A 4:1 mux can be implemented using two 2:1 muxes by selecting one of the 2:1 muxes based on the select line.
Use one 2:1 mux to select between the two inputs of the second 2:1 mux based on the select line
Connect the outputs of the two 2:1 muxes to get the final 4:1 mux output
A 58:1 mux can be implemented using 2:1 mux by cascading multiple levels of muxes.
Implement a 2:1 mux using 2 input lines and 1 output line.
Cascading multiple levels of 2:1 muxes can create a 4:1, 8:1, 16:1, and finally a 58:1 mux.
In this case, you would need 6 levels of 2:1 muxes to create a 58:1 mux.
posted on 18 Aug 2024
I applied via Campus Placement and was interviewed in Jul 2024. There were 3 interview rounds.
Basic Aptitude question
posted on 18 Aug 2024
I applied via Referral and was interviewed in Feb 2024. There were 3 interview rounds.
Qustions are simple mostly are time and work , sequence detector,probability
posted on 27 Feb 2024
I applied via campus placement at Birla Institute of Technology and Science (BITS), Pilani and was interviewed in Aug 2023. There were 2 interview rounds.
Easy aptitude test of 20qs.
posted on 15 Feb 2024
I applied via campus placement at Birla Institute of Technology and Science (BITS), Pilani and was interviewed before Feb 2023. There were 2 interview rounds.
Texas came to TIER 1 college in day 0 of placement. Written questions were pretty much on the higher side of difficulty. Need to practice and apply concepts smartly, no need to mug up formulas unnecessarily.
posted on 3 Dec 2022
I applied via campus placement at Indian Institute of Technology (IIT), Mumbai and was interviewed in Nov 2022. There was 1 interview round.
Count the number of one's in a vector.
Iterate through the vector and count the number of ones encountered.
Use built-in functions like count() or accumulate() in C++.
In Python, use the count() method or sum() function with a conditional statement.
Design a circuit to detect a pattern
Define the pattern to be detected
Choose appropriate sensors to detect the pattern
Use logic gates to process the sensor data
Output a signal when the pattern is detected
posted on 19 May 2022
I applied via campus placement at Birla Institute of Technology and Science (BITS), Pilani and was interviewed before May 2021. There were 3 interview rounds.
posted on 3 Mar 2015
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