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Tessolve Semiconductor Digital Design Engineer Interview Questions and Answers

Updated 1 Dec 2024

Tessolve Semiconductor Digital Design Engineer Interview Experiences

1 interview found

Interview experience
3
Average
Difficulty level
Moderate
Process Duration
Less than 2 weeks
Result
No response

I applied via campus placement at Indian School of Mines (ISM), Dhanbad and was interviewed in Nov 2024. There was 1 interview round.

Round 1 - Technical 

(4 Questions)

  • Q1. Implement nand gate using 2:1 mux
  • Ans. 

    NAND gate can be implemented using a 2:1 multiplexer by connecting one input to select line and the other input to one of the data inputs.

    • Connect one input of the NAND gate to the select line of the 2:1 mux.

    • Connect the other input of the NAND gate to one of the data inputs of the 2:1 mux.

    • Connect the other data input of the 2:1 mux to ground.

    • The output of the 2:1 mux will be the output of the NAND gate.

  • Answered by AI
  • Q2. Implement a 4:1 mux using 2:1 mux
  • Ans. 

    A 4:1 mux can be implemented using two 2:1 muxes by selecting one of the 2:1 muxes based on the select line.

    • Use one 2:1 mux to select between the two inputs of the second 2:1 mux based on the select line

    • Connect the outputs of the two 2:1 muxes to get the final 4:1 mux output

  • Answered by AI
  • Q3. Implement a 58:1 mux using 2:1 mux and how many mux are required?
  • Ans. 

    A 58:1 mux can be implemented using 2:1 mux by cascading multiple levels of muxes.

    • Implement a 2:1 mux using 2 input lines and 1 output line.

    • Cascading multiple levels of 2:1 muxes can create a 4:1, 8:1, 16:1, and finally a 58:1 mux.

    • In this case, you would need 6 levels of 2:1 muxes to create a 58:1 mux.

  • Answered by AI
  • Q4. Projects in the resume

Interview Preparation Tips

Interview preparation tips for other job seekers - Basics are very important as the interview was only around the basic digital circuits

Interview questions from similar companies

Interview experience
5
Excellent
Difficulty level
Moderate
Process Duration
Less than 2 weeks
Result
Selected Selected

I applied via Campus Placement and was interviewed in Jul 2024. There were 3 interview rounds.

Round 1 - Aptitude Test 

Basic Aptitude question

Round 2 - Technical 

(1 Question)

  • Q1. Included basic level of digital design concepts
Round 3 - One-on-one 

(1 Question)

  • Q1. Multiplexers,clock divider
Interview experience
4
Good
Difficulty level
Moderate
Process Duration
Less than 2 weeks
Result
Not Selected

I applied via Referral and was interviewed in Feb 2024. There were 3 interview rounds.

Round 1 - Aptitude Test 

Qustions are simple mostly are time and work , sequence detector,probability

Round 2 - Technical 

(3 Questions)

  • Q1. They asked about the related from counter ,flip flops
  • Q2. Simple question from combinational circuit
  • Q3. Asked about Flipflops
Round 3 - Technical 

(2 Questions)

  • Q1. Asked Cmos structure, equations
  • Q2. Project + Verilog questions
Interview experience
4
Good
Difficulty level
Moderate
Process Duration
Less than 2 weeks
Result
Selected Selected

I applied via campus placement at Birla Institute of Technology and Science (BITS), Pilani and was interviewed in Aug 2023. There were 2 interview rounds.

Round 1 - Aptitude Test 

Easy aptitude test of 20qs.

Round 2 - Technical 

(1 Question)

  • Q1. Basic STA questions.
Interview experience
5
Excellent
Difficulty level
Hard
Process Duration
Less than 2 weeks
Result
Selected Selected

I applied via campus placement at Birla Institute of Technology and Science (BITS), Pilani and was interviewed before Feb 2023. There were 2 interview rounds.

Round 1 - Aptitude Test 

Texas came to TIER 1 college in day 0 of placement. Written questions were pretty much on the higher side of difficulty. Need to practice and apply concepts smartly, no need to mug up formulas unnecessarily.

Round 2 - Technical 

(1 Question)

  • Q1. They will grill you with whatever you have written in your resume so far. I was asked multiple design level questions so far.

I applied via campus placement at Indian Institute of Technology (IIT), Mumbai and was interviewed in Nov 2022. There was 1 interview round.

Round 1 - Technical 

(2 Questions)

  • Q1. Count the number of one's in the vector
  • Ans. 

    Count the number of one's in a vector.

    • Iterate through the vector and count the number of ones encountered.

    • Use built-in functions like count() or accumulate() in C++.

    • In Python, use the count() method or sum() function with a conditional statement.

  • Answered by AI
  • Q2. Design a circuit to detect a pattern
  • Ans. 

    Design a circuit to detect a pattern

    • Define the pattern to be detected

    • Choose appropriate sensors to detect the pattern

    • Use logic gates to process the sensor data

    • Output a signal when the pattern is detected

  • Answered by AI

Interview Preparation Tips

Interview preparation tips for other job seekers - Be thorough with basic digital design and FSMs. Practice from HDLBITS

Skills evaluated in this interview

I applied via campus placement at Birla Institute of Technology and Science (BITS), Pilani and was interviewed before May 2021. There were 3 interview rounds.

Round 1 - Resume Shortlist 
Pro Tip by AmbitionBox:
Keep your resume crisp and to the point. A recruiter looks at your resume for an average of 6 seconds, make sure to leave the best impression.
View all tips
Round 2 - Technical 

(1 Question)

  • Q1. The round 2 consisted of aptitude , digital and analog section. A person needs to atrempt the section based on the profile they wanted to apply for
Round 3 - One-on-one 

(1 Question)

  • Q1. The questions were mainly related to basics of digital design and approach to questions was the major thing focused in the entire interview.

Interview Preparation Tips

Topics to prepare for Texas Instruments Digital Design Engineer interview:
  • Digital design
  • Embedded system
  • Computer Architecture
Interview preparation tips for other job seekers - Basics matter a lot in digital as well as for analog interviews. If you are confident in your answers then it leads a really good impact on interviewer.

Interview Preparation Tips

Round: Test
Experience: There was written test in the very beginning of the selection process. It had questions from logical reasoning, quantitative aptitude and electronics. It had questions from microprocessor and many other electronics topic. Thereafter there were the interview rounds.

Round: HR Interview
Experience: There were 2 rounds in which they asked me both HR questions as well as core field related question. They asked me to describe myself as well as tell them about my strengths and weaknesses. They also asked me about working in the southern part of India and my views on relocation.

On the technical side they asked me the following questions:

1) Design of D-latch from 2*1 mux?
2) XOR gate using minimum number of NAND gates?
3) Shift registers connections to get a particular sequence?
4) Use of Accumulator in processors like 8085?

In general the interview was more focussed on the technical side with the HR side just to make sure I will be a good fit in the company.

College Name: IIT KANPUR

Tessolve Semiconductor Interview FAQs

How many rounds are there in Tessolve Semiconductor Digital Design Engineer interview?
Tessolve Semiconductor interview process usually has 1 rounds. The most common rounds in the Tessolve Semiconductor interview process are Technical.
What are the top questions asked in Tessolve Semiconductor Digital Design Engineer interview?

Some of the top questions asked at the Tessolve Semiconductor Digital Design Engineer interview -

  1. Implement a 58:1 mux using 2:1 mux and how many mux are requir...read more
  2. Implement nand gate using 2:1 ...read more
  3. Implement a 4:1 mux using 2:1 ...read more

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