Sion Semiconductors Soc Verification Intern Interview Questions and Answers

Q1. Basic question of sv like swapping no.
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Q2. Question from projects
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Q1. Assertions and coverage
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Q2. Umv basic principle
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UVM (Universal Verification Methodology) basic principle is to provide a standardized methodology for verifying digital designs.
• UVM is based on SystemVerilog and provides a framework for creating reusable verification environments

• It promotes the use of object-oriented programming techniques for creating modular and scalable testbenches

• UVM encourages the use of constrained-random stimulus generation and coverage-driven ...read more
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Q1. They asked from Digital, COA
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Q1. They asked the concepts of COA
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Q1. First started with Puzzle and then about company
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Q1. Basics of analog , digital and vlsi
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Q2. On face to face interview, they asked me abt my projects , digital, little analog , vlsi ( verilog), microcontrollers and c programming
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Q1. The question was draw cmos inverter transfer characteristics and by varying some parameters they asked their effects on it.
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It was good and easy as well

Q1. What is polymorphism explain with an example
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Polymorphism is the ability of a function or method to behave differently based on the object it is called with.
• Polymorphism allows objects of different classes to be treated as objects of a common superclass.

• There are two types of polymorphism: compile-time (method overloading) and runtime (method overriding).

• Example: Animal superclass with methods like eat() and sleep(), and subclasses like Dog and Cat that override
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Q1. Asked the working experience and the related skills to the new job
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Q1. Coding questions in Verilog, Systemverilog, random constraints such as how to write a onehot in different ways
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Q1. Asked the expectation of the base salary and overall compensation
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