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posted on 8 Oct 2024
I am a passionate and detail-oriented Design & Verification Engineer with a strong background in digital design and verification methodologies.
Experienced in RTL design and verification using Verilog and SystemVerilog
Proficient in using industry-standard EDA tools such as Synopsys VCS and Cadence Incisive
Familiar with UVM methodology for verification
Strong problem-solving skills and ability to work in a team environmen
Quantitive Aptitude, Digital Electronics, Memory
Simple and Moderate have to practice
Simple and Moderate exam
I was interviewed in Mar 2024.
Basic aptitude questions
Digital electronics questions(6), verilog questions(2), sv questions(2), uvm questions(2)
Sion Semiconductors interview questions for popular designations
I applied via Referral and was interviewed in Feb 2024. There was 1 interview round.
Counters, frequency divider circuit, MUX, behavioural modelling
I applied via LinkedIn and was interviewed in Jan 2024. There was 1 interview round.
1.based on work and time
2.based on trains
3.based on relations
Top trending discussions
I was interviewed in Jan 2025.
Arrays and string kind of DSA questions
posted on 10 Dec 2024
I applied via LinkedIn and was interviewed in Nov 2024. There were 3 interview rounds.
I applied via Naukri.com and was interviewed in Sep 2024. There were 3 interview rounds.
Runtime polymorphism in C++ is achieved through virtual functions, vptr (virtual pointer), and vtable (virtual table).
Runtime polymorphism allows objects of different classes to be treated as objects of a common superclass.
Virtual functions are declared in a base class and overridden in derived classes to achieve polymorphism.
vptr is a pointer that points to the vtable of an object, allowing dynamic binding of virtual ...
I primarily use C++17, but I am familiar with earlier versions as well.
I am comfortable working with features introduced in C++17 such as structured bindings and constexpr if
I have experience with earlier versions like C++11 and C++14
I stay updated with the latest features and improvements in C++ standards
Yes, I have used Windows API's extensively in my previous projects.
I have used Windows API's for tasks such as creating windows, handling messages, and interacting with system resources.
Examples include using functions like CreateWindow, SendMessage, and ReadFile.
I have also worked with specific Windows API's like Winsock for networking and WinINet for internet-related tasks.
dynamic_cast is a C++ operator used for safe downcasting of pointers and references in polymorphic classes.
dynamic_cast is used to safely downcast a pointer or reference from a base class to a derived class.
It can fail if the object being casted is not of the target type, in which case it returns a null pointer for pointers or throws a std::bad_cast exception for references.
Dynamic_cast can only be used with pointers o...
Union in C++ is a data structure that allows storing different data types in the same memory location.
Unions are similar to structures but all members share the same memory location.
Only one member of a union can be accessed at a time.
Unions are useful when you need to store different data types in the same memory space.
Example: union MyUnion { int i; float f; };
Example: MyUnion u; u.i = 10; // Accessing integer member
Weak pointer is a type of smart pointer in C++ that does not control the lifetime of the object it points to.
Weak pointers are used to break circular references in shared pointers.
They do not increase the reference count of the object.
They are used in scenarios where the object may be deleted while there are still weak pointers pointing to it.
Processes and threads are units of execution in a computer system. Memory is allocated to processes. Mutex and semaphore are synchronization mechanisms. Core refers to a processing unit in a multi-core system. Context switching is the process of switching between different processes or threads.
Processes are independent units of execution with their own memory space and resources.
Threads are lightweight units of executi...
I was interviewed in Dec 2024.
based on 10 interviews
Interview experience
based on 40 reviews
Rating in categories
Design & Verification Engineer
13
salaries
| ₹1 L/yr - ₹9.6 L/yr |
Design and Verification Intern
8
salaries
| ₹1 L/yr - ₹3 L/yr |
RTL Design Engineer
6
salaries
| ₹4.5 L/yr - ₹18 L/yr |
Verification Engineer
5
salaries
| ₹2 L/yr - ₹4.5 L/yr |
Embedded Design Engineer
4
salaries
| ₹4 L/yr - ₹6.5 L/yr |
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