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InSemi Technology Services Interview Questions and Answers

Updated 25 Mar 2025
Popular Designations

13 Interview questions

A Design & Verification Engineer was asked 7mo ago
Q. What are the different types of transitions in PCIe?
Ans. 

There are three types of transitions in PCIe: TLP (Transaction Layer Packet) Data, TLP Address, and DLLP (Data Link Layer Packet).

  • TLP (Transaction Layer Packet) Data transition carries payload data from the sender to the receiver.

  • TLP Address transition contains the address information of the data being transmitted.

  • DLLP (Data Link Layer Packet) transition is used for flow control and error handling.

View all Design & Verification Engineer interview questions
A Design & Verification Engineer was asked 7mo ago
Q. Describe your experience with test bench environments for FIFO.
Ans. 

Test bench environment for FIFO involves creating stimuli to test the functionality of a FIFO design.

  • Create stimulus to write data into the FIFO

  • Create stimulus to read data from the FIFO

  • Implement checks to verify data integrity and order

  • Randomize data inputs to test different scenarios

  • Monitor FIFO status signals for debugging

View all Design & Verification Engineer interview questions
A Design & Verification Engineer was asked 7mo ago
Q. 4x4 matrix representation with diagonal elements are 5 multiples
Ans. 

A 4x4 matrix with diagonal elements as multiples of 5.

  • Diagonal elements: [5, 10, 15, 20]

  • Non-diagonal elements can be any value

  • Example matrix: [[5, 2, 3, 4], [1, 10, 6, 7], [8, 9, 15, 11], [12, 13, 14, 20]]

View all Design & Verification Engineer interview questions
A Senior Design Engineer was asked 12mo ago
Q. How do you swap two variables?
Ans. 

Swapping the values of two variables without using a temporary variable.

  • Use XOR operation to swap two variables without using a temporary variable.

  • Example: a = 5, b = 10. After swapping, a = 10, b = 5.

View all Senior Design Engineer interview questions
An Analog Layout Engineer was asked 12mo ago
Q. What are some ways to solve antenna issues?
Ans. 

Antenna issues can be solved by proper layout techniques and design considerations.

  • Ensure proper spacing between antenna and other components to reduce interference

  • Use shielding techniques like ground planes or metal layers to minimize radiation

  • Optimize the shape and size of the antenna for better performance

  • Avoid sharp corners or discontinuities in the antenna layout

  • Perform simulations and testing to validate the...

View all Analog Layout Engineer interview questions
A Validation Engineer was asked 12mo ago
Q. What is an interrupt, and can you explain ISR?
Ans. 

An interrupt is a signal sent to the CPU to alert it of an event that needs immediate attention. ISR stands for Interrupt Service Routine, which is a function that handles the interrupt.

  • Interrupt is a mechanism used by hardware devices to request attention from the CPU.

  • ISR is a specific routine that is executed in response to an interrupt.

  • ISRs are used to handle events that require immediate attention, such as har...

View all Validation Engineer interview questions
A Design & Verification Engineer was asked
Q. What are the basics of IVM and SV?
Ans. 

IVM (Interleaved Verification Method) and SV (SystemVerilog) are essential concepts in design verification.

  • IVM is a methodology that allows for concurrent verification of multiple design scenarios.

  • SV is a hardware description and verification language that extends Verilog with object-oriented features.

  • IVM helps in reducing simulation time by interleaving different test scenarios.

  • SV supports advanced verification t...

View all Design & Verification Engineer interview questions
Are these interview questions helpful?
A Design Engineer was asked
Q. Implement an AND gate using a 4:2 multiplexer.
Ans. 

An AND gate can be implemented using a 4:2 MUX by connecting the inputs to the select lines and the outputs to the MUX inputs.

  • Connect the two inputs to the select lines of the MUX

  • Connect one of the MUX inputs to Vcc and the other to ground

  • Connect the output of the MUX to the AND gate output

  • The truth table of the AND gate can be implemented using the truth table of the MUX

  • Example: If the select lines are 00, the ou...

View all Design Engineer interview questions
An Engineering Intern was asked
Q. What is the difference between a latch and a flip-flop?
Ans. 

Latch is level triggered and stores data while enabled. Flip-flop is edge triggered and stores data on clock signal.

  • Latch is asynchronous while flip-flop is synchronous

  • Latch has only one input while flip-flop has two inputs

  • SR latch, D latch, and JK latch are examples of latches

  • D flip-flop, JK flip-flop, and T flip-flop are examples of flip-flops

View all Engineering Intern interview questions
A Senior Dft Engineer was asked 12mo ago
Q. What are the DRCs I have faced, simulation debugs etc.
Ans. 

I have faced various DRCs and simulation debugs in my experience as a Senior DFT Engineer.

  • I have encountered DRCs related to clock domain crossing issues

  • I have debugged simulation mismatches between RTL and gate-level netlists

  • I have resolved DRC violations related to scan chain connectivity

  • I have optimized scan chain insertion to meet timing constraints

View all Senior Dft Engineer interview questions

InSemi Technology Services Interview Experiences

14 interviews found

Interview experience
4
Good
Difficulty level
-
Process Duration
-
Result
-
Round 1 - Technical 

(2 Questions)

  • Q1. About PCIe protocal
  • Q2. 4x4 matrix representation with diagonal elements are 5 multiples
  • Ans. 

    A 4x4 matrix with diagonal elements as multiples of 5.

    • Diagonal elements: [5, 10, 15, 20]

    • Non-diagonal elements can be any value

    • Example matrix: [[5, 2, 3, 4], [1, 10, 6, 7], [8, 9, 15, 11], [12, 13, 14, 20]]

  • Answered by AI
Round 2 - Technical 

(2 Questions)

  • Q1. Test bench environment for fifo
  • Ans. 

    Test bench environment for FIFO involves creating stimuli to test the functionality of a FIFO design.

    • Create stimulus to write data into the FIFO

    • Create stimulus to read data from the FIFO

    • Implement checks to verify data integrity and order

    • Randomize data inputs to test different scenarios

    • Monitor FIFO status signals for debugging

  • Answered by AI
  • Q2. Types of transitions in pcie
  • Ans. 

    There are three types of transitions in PCIe: TLP (Transaction Layer Packet) Data, TLP Address, and DLLP (Data Link Layer Packet).

    • TLP (Transaction Layer Packet) Data transition carries payload data from the sender to the receiver.

    • TLP Address transition contains the address information of the data being transmitted.

    • DLLP (Data Link Layer Packet) transition is used for flow control and error handling.

  • Answered by AI

Skills evaluated in this interview

Interview experience
5
Excellent
Difficulty level
-
Process Duration
-
Result
-
Round 1 - Technical 

(2 Questions)

  • Q1. First interview is like a screening round and mostly questions were based on my work.
  • Q2. What are the DRCs I have faced, simulation debugs etc.
  • Ans. 

    I have faced various DRCs and simulation debugs in my experience as a Senior DFT Engineer.

    • I have encountered DRCs related to clock domain crossing issues

    • I have debugged simulation mismatches between RTL and gate-level netlists

    • I have resolved DRC violations related to scan chain connectivity

    • I have optimized scan chain insertion to meet timing constraints

  • Answered by AI
Round 2 - Technical 

(3 Questions)

  • Q1. Scan compression questions were asked
  • Q2. Cascaded occ concept
  • Q3. Timing simulation debug

Interview Preparation Tips

Interview preparation tips for other job seekers - Mostly be clear for the work you have done and be confident in that. Basics should be clear.

Skills evaluated in this interview

Interview experience
5
Excellent
Difficulty level
Moderate
Process Duration
2-4 weeks
Result
-

I appeared for an interview in Feb 2025, where I was asked the following questions.

  • Q1. C programing and theory
  • Q2. Mc protocols and project explanation
  • Ans. 

    MC protocols manage communication in embedded systems, ensuring efficient data transfer and resource allocation.

    • MC protocols stand for Medium Access Control protocols, crucial in networked embedded systems.

    • Examples include ALOHA, CSMA/CD, and TDMA, each with unique methods for managing access to shared communication channels.

    • In wireless sensor networks, MC protocols help reduce collisions and improve energy efficiency.

    • ...

  • Answered by AI
Interview experience
4
Good
Difficulty level
-
Process Duration
-
Result
-
Round 1 - Technical 

(2 Questions)

  • Q1. What type of debug done in your project ?
  • Q2. What is interrupt and explain isr ?
  • Ans. 

    An interrupt is a signal sent to the CPU to alert it of an event that needs immediate attention. ISR stands for Interrupt Service Routine, which is a function that handles the interrupt.

    • Interrupt is a mechanism used by hardware devices to request attention from the CPU.

    • ISR is a specific routine that is executed in response to an interrupt.

    • ISRs are used to handle events that require immediate attention, such as hardware...

  • Answered by AI
Round 2 - Coding Test 

Programs on bit wise operators

Skills evaluated in this interview

Senior Design Engineer Interview Questions & Answers

user image Pushpak Chaudhari

posted on 17 Jun 2024

Interview experience
5
Excellent
Difficulty level
-
Process Duration
-
Result
Selected Selected
Round 1 - Technical 

(2 Questions)

  • Q1. Swaping of 2 variables
  • Ans. 

    Swapping the values of two variables without using a temporary variable.

    • Use XOR operation to swap two variables without using a temporary variable.

    • Example: a = 5, b = 10. After swapping, a = 10, b = 5.

  • Answered by AI
  • Q2. Implementation of protocol
  • Ans. 

    Implementation of protocol involves defining rules and procedures for communication between devices or systems.

    • Define the purpose and scope of the protocol

    • Specify the format and structure of data to be exchanged

    • Establish rules for error detection and correction

    • Implement protocol using programming languages like C, Python, or Java

    • Test the protocol for interoperability and performance

  • Answered by AI

Skills evaluated in this interview

Interview experience
5
Excellent
Difficulty level
-
Process Duration
-
Result
-
Round 1 - One-on-one 

(2 Questions)

  • Q1. Ways to slove antenna ?
  • Ans. 

    Antenna issues can be solved by proper layout techniques and design considerations.

    • Ensure proper spacing between antenna and other components to reduce interference

    • Use shielding techniques like ground planes or metal layers to minimize radiation

    • Optimize the shape and size of the antenna for better performance

    • Avoid sharp corners or discontinuities in the antenna layout

    • Perform simulations and testing to validate the ante...

  • Answered by AI
  • Q2. Jumpers & reverse connected diode near to gate.
Interview experience
4
Good
Difficulty level
-
Process Duration
-
Result
-
Round 1 - Resume Shortlist 
Pro Tip by AmbitionBox:
Keep your resume crisp and to the point. A recruiter looks at your resume for an average of 6 seconds, make sure to leave the best impression.
View all tips
Round 2 - Technical 

(2 Questions)

  • Q1. Verilog- blocking and non blocking, data types
  • Q2. System verilog-areays and its types, task and function
  • Ans. 

    SystemVerilog arrays are data structures that store multiple elements of the same data type. Tasks and functions are reusable blocks of code.

    • SystemVerilog arrays can be declared using the 'array' keyword, with different types like dynamic arrays, associative arrays, and queues.

    • Tasks are reusable blocks of code that can contain a sequence of statements and can be called multiple times within a module.

    • Functions are simil...

  • Answered by AI
Round 3 - Technical 

(1 Question)

  • Q1. Basics of ivm and sv
  • Ans. 

    IVM (Interleaved Verification Method) and SV (SystemVerilog) are essential concepts in design verification.

    • IVM is a methodology that allows for concurrent verification of multiple design scenarios.

    • SV is a hardware description and verification language that extends Verilog with object-oriented features.

    • IVM helps in reducing simulation time by interleaving different test scenarios.

    • SV supports advanced verification techni...

  • Answered by AI
Round 4 - Aptitude Test 

Ants move in triangular, whats the possibility of not moving opposite to each other

Interview Preparation Tips

Interview preparation tips for other job seekers - Sound knowledge in basics of verilog, sv,uvm

Skills evaluated in this interview

Interview experience
4
Good
Difficulty level
Easy
Process Duration
Less than 2 weeks
Result
No response

I applied via LinkedIn and was interviewed in Jan 2024. There was 1 interview round.

Round 1 - Technical 

(1 Question)

  • Q1. Verilog topics : blocking, NB ,delays Digital : Mux, decoders, sequential logic

Design Engineer Interview Questions & Answers

user image YASHWANTH DANDU

posted on 3 Jan 2023

Interview experience
4
Good
Difficulty level
Hard
Process Duration
2-4 weeks
Result
Selected Selected

I applied via LinkedIn and was interviewed in Dec 2022. There were 4 interview rounds.

Round 1 - Resume Shortlist 
Pro Tip by AmbitionBox:
Keep your resume crisp and to the point. A recruiter looks at your resume for an average of 6 seconds, make sure to leave the best impression.
View all tips
Round 2 - Technical 

(1 Question)

  • Q1. VLSI Based Questions Digital Electronic Questions Digital Gates
Round 3 - Technical 

(1 Question)

  • Q1. CMOS Concept VLSI Design Fabrication
Round 4 - HR 

(1 Question)

  • Q1. Realted Company Questions & HR Policy Terms

Interview Preparation Tips

Topics to prepare for InSemi Technology Services Design Engineer interview:
  • Digital Electronics
  • Digital Gates
  • VLSI Basics
  • Network Theory
  • Circuit Analysis
  • Lab Experience Basics
Interview preparation tips for other job seekers - We should know all Basic conceps in dept regarding to your Applied Position.
Interview experience
5
Excellent
Difficulty level
-
Process Duration
-
Result
-
Round 1 - Resume Shortlist 
Pro Tip by AmbitionBox:
Don’t add your photo or details such as gender, age, and address in your resume. These details do not add any value.
View all tips
Round 2 - Technical 

(2 Questions)

  • Q1. So many related to subject
  • Q2. SV UVM verilog and digital
Round 3 - Technical 

(1 Question)

  • Q1. All related to subject

Interview Preparation Tips

Interview preparation tips for other job seekers - Prepare well for interview stick to basics.
Best of luck.

Top trending discussions

View All
Interview Tips & Stories
1w (edited)
a team lead
Why are women still asked such personal questions in interview?
I recently went for an interview… and honestly, m still trying to process what just happened. Instead of being asked about my skills, experience, or how I could add value to the company… the questions took a totally unexpected turn. The interviewer started asking things like When are you getting married? Are you engaged? And m sure, if I had said I was married, the next question would’ve been How long have you been married? What does my personal life have to do with the job m applying for? This is where I felt the gender discrimination hit hard. These types of questions are so casually thrown at women during interviews but are they ever asked to men? No one asks male candidates if they’re planning a wedding or how old their kids are. So why is it okay to ask women? Can we please stop normalising this kind of behaviour in interviews? Our careers shouldn’t be judged by our relationship status. Period.
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InSemi Technology Services Interview FAQs

How many rounds are there in InSemi Technology Services interview?
InSemi Technology Services interview process usually has 2-3 rounds. The most common rounds in the InSemi Technology Services interview process are Technical, HR and Resume Shortlist.
How to prepare for InSemi Technology Services interview?
Go through your CV in detail and study all the technologies mentioned in your CV. Prepare at least two technologies or languages in depth if you are appearing for a technical interview at InSemi Technology Services. The most common topics and skills that interviewers at InSemi Technology Services expect are Python, Perl, Debugging, C++ and Physical Design.
What are the top questions asked in InSemi Technology Services interview?

Some of the top questions asked at the InSemi Technology Services interview -

  1. What are the DRCs I have faced, simulation debugs e...read more
  2. 4x4 matrix representation with diagonal elements are 5 multip...read more
  3. System verilog-areays and its types, task and funct...read more

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Overall Interview Experience Rating

4.5/5

based on 13 interview experiences

Difficulty level

Easy 33%
Moderate 33%
Hard 33%

Duration

Less than 2 weeks 33%
2-4 weeks 67%
View more

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InSemi Technology Services Reviews and Ratings

based on 79 reviews

3.7/5

Rating in categories

3.5

Skill development

3.8

Work-life balance

3.2

Salary

3.4

Job security

3.6

Company culture

3.1

Promotions

3.4

Work satisfaction

Explore 79 Reviews and Ratings
Mac Os Developer

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