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A 4x4 matrix with diagonal elements as multiples of 5.
Diagonal elements: [5, 10, 15, 20]
Non-diagonal elements can be any value
Example matrix: [[5, 2, 3, 4], [1, 10, 6, 7], [8, 9, 15, 11], [12, 13, 14, 20]]
Test bench environment for FIFO involves creating stimuli to test the functionality of a FIFO design.
Create stimulus to write data into the FIFO
Create stimulus to read data from the FIFO
Implement checks to verify data integrity and order
Randomize data inputs to test different scenarios
Monitor FIFO status signals for debugging
There are three types of transitions in PCIe: TLP (Transaction Layer Packet) Data, TLP Address, and DLLP (Data Link Layer Packet).
TLP (Transaction Layer Packet) Data transition carries payload data from the sender to the receiver.
TLP Address transition contains the address information of the data being transmitted.
DLLP (Data Link Layer Packet) transition is used for flow control and error handling.
SystemVerilog arrays are data structures that store multiple elements of the same data type. Tasks and functions are reusable blocks of code.
SystemVerilog arrays can be declared using the 'array' keyword, with different types like dynamic arrays, associative arrays, and queues.
Tasks are reusable blocks of code that can contain a sequence of statements and can be called multiple times within a module.
Functions are simil...
Ants move in triangular, whats the possibility of not moving opposite to each other
I applied via LinkedIn and was interviewed in Jan 2024. There was 1 interview round.
InSemi Technology Services interview questions for designations
I applied via Campus Placement and was interviewed in Mar 2022. There were 4 interview rounds.
It had write up test, questions were so basic related to digital electronics, verilog, pseudo codes of C, aptitude.
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3-6 Yrs
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Design Engineer
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Senior Design Engineer
45
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Verification Engineer
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Physical Design Engineer
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Associate Verification Engineer
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