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I applied via LinkedIn and was interviewed in Dec 2022. There were 4 interview rounds.
I applied via Campus Placement and was interviewed in Apr 2022. There were 2 interview rounds.
Written test
An AND gate can be implemented using a 4:2 MUX by connecting the inputs to the select lines and the outputs to the MUX inputs.
Connect the two inputs to the select lines of the MUX
Connect one of the MUX inputs to Vcc and the other to ground
Connect the output of the MUX to the AND gate output
The truth table of the AND gate can be implemented using the truth table of the MUX
Example: If the select lines are 00, the output
Top trending discussions
posted on 20 Aug 2024
I applied via campus placement at B M S College of Engineering, Bangalore and was interviewed in Jul 2024. There were 2 interview rounds.
Asked Basic Aptitude Questions
ASICs are custom-designed for specific applications, while FPGAs are reprogrammable and more flexible.
ASICs are Application-Specific Integrated Circuits designed for a specific purpose or application.
FPGAs are Field-Programmable Gate Arrays that can be reconfigured for different tasks.
ASICs are more efficient and faster than FPGAs for specific tasks.
FPGAs are more flexible and can be reprogrammed for different function...
posted on 20 Aug 2024
I applied via campus placement at B M S College of Engineering, Bangalore and was interviewed in Jul 2024. There were 2 interview rounds.
Asked Basic Aptitude Questions
ASICs are custom-designed for specific applications, while FPGAs are reprogrammable and more flexible.
ASICs are Application-Specific Integrated Circuits designed for a specific purpose or application.
FPGAs are Field-Programmable Gate Arrays that can be reconfigured for different tasks.
ASICs are more efficient and faster than FPGAs for specific tasks.
FPGAs are more flexible and can be reprogrammed for different function...
posted on 17 May 2024
I applied via Approached by Company and was interviewed in Nov 2023. There was 1 interview round.
Interview experience
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