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I applied via Campus Placement and was interviewed in Mar 2022. There were 4 interview rounds.
It had write up test, questions were so basic related to digital electronics, verilog, pseudo codes of C, aptitude.
Technical assessment
Latch is level triggered and stores data while enabled. Flip-flop is edge triggered and stores data on clock signal.
Latch is asynchronous while flip-flop is synchronous
Latch has only one input while flip-flop has two inputs
SR latch, D latch, and JK latch are examples of latches
D flip-flop, JK flip-flop, and T flip-flop are examples of flip-flops
I applied via Campus Placement and was interviewed in Apr 2022. There were 2 interview rounds.
Written test
An AND gate can be implemented using a 4:2 MUX by connecting the inputs to the select lines and the outputs to the MUX inputs.
Connect the two inputs to the select lines of the MUX
Connect one of the MUX inputs to Vcc and the other to ground
Connect the output of the MUX to the AND gate output
The truth table of the AND gate can be implemented using the truth table of the MUX
Example: If the select lines are 00, the output
I applied via Campus Placement and was interviewed in Mar 2021. There were 3 interview rounds.
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