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Alphawave Semi
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I applied via Recruitment Consulltant and was interviewed in May 2024. There were 3 interview rounds.
Online Test which consists of Aptitude, Reasoning, Electronic Circuits and PD questions
Physical Design flow involves multiple stages with various checks to ensure design quality and manufacturability.
Synthesis: Logic synthesis to convert RTL to gate-level netlist.
Floorplanning: Define chip area, placement of blocks, and power grid.
Placement: Place standard cells in the floorplan area.
Clock Tree Synthesis: Build clock distribution network for timing.
Routing: Connect the placed cells with metal layers.
Desi...
I am a dedicated and experienced Physical Design Engineer with a strong background in designing and optimizing integrated circuits.
I have a Bachelor's degree in Electrical Engineering from XYZ University.
I have worked at ABC Semiconductor for 5 years, where I led the physical design team for multiple successful projects.
I am proficient in tools like Cadence Virtuoso and Synopsys ICC.
I have a strong understanding of tim...
NAND gate can be implemented using CMOS technology, which involves using both NMOS and PMOS transistors in parallel.
NAND gate consists of multiple transistors connected in series and parallel to achieve the desired logic function.
In CMOS implementation, NMOS transistors are used for the pull-down network while PMOS transistors are used for the pull-up network.
When any of the inputs is low, the corresponding NMOS transi...
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posted on 14 Oct 2024
I applied via Referral and was interviewed in Sep 2024. There were 2 interview rounds.
posted on 31 Oct 2024
I applied via Walk-in and was interviewed in Oct 2024. There were 3 interview rounds.
posted on 21 Nov 2024
I applied via Recruitment Consulltant and was interviewed in Oct 2024. There were 3 interview rounds.
We have 25 questions and negative marking is there
Storage classes in C language define the scope and lifetime of variables.
There are four storage classes in C: auto, register, static, and extern.
Auto variables are local to the block they are declared in and have automatic storage duration.
Register variables are stored in CPU registers for faster access.
Static variables retain their value between function calls.
Extern variables are declared outside of any function and ...
There are 10 address lines present in 1kb memory.
1kb memory = 1024 bytes
To address 1024 bytes, 10 address lines are needed (2^10 = 1024)
Reverse an array of strings
Create a new array to store the reversed strings
Iterate through the original array in reverse order and add each element to the new array
Return the new array as the reversed array
posted on 26 Nov 2024
I was interviewed in Oct 2024.
The PD flow is the process of designing the physical layout of integrated circuits.
Initial floorplanning to determine the placement of blocks and macros
Placement and optimization of standard cells
Routing of interconnects to connect the various components
Physical verification to ensure design rules are met
Timing closure to meet performance targets
Setup and hold violations can be fixed by adjusting timing constraints, optimizing clock tree, and redesigning critical paths.
Adjust timing constraints to allow more time for signals to propagate
Optimize clock tree to reduce clock skew and improve timing
Redesign critical paths by adding buffers or restructuring logic
Use ECO (Engineering Change Order) to make necessary changes without redoing the entire design
My domain expertise is in physical design engineering, specifically in the areas of floorplanning, placement, routing, and timing closure.
Floorplanning
Placement
Routing
Timing closure
Setup and hold time violations can occur on the same path due to different reasons.
Timing violations can occur due to variations in process, voltage, and temperature (PVT)
Clock skew between different paths can lead to setup and hold violations on the same path
Issues with clock tree synthesis or routing can also contribute to setup and hold time violations
Improper constraints or incorrect timing analysis setup can resul
I am asked to give the coding test and tech questions on resume and job description
posted on 25 Oct 2024
I applied via campus placement at RV College Of Engineering (RVCE) and was interviewed in Sep 2024. There were 3 interview rounds.
General aptitude questions. Easy to solve. Didn’t take much time
An RC circuit consists of a resistor and a capacitor connected in series or parallel, used for filtering, timing, and signal processing.
RC circuit operation is based on the charging and discharging of the capacitor through the resistor.
When a voltage is applied to the circuit, the capacitor charges up to the applied voltage through the resistor.
The time constant (RC) determines how quickly the capacitor charges or disc...
A diode waveform typically shows a voltage drop when forward biased and no current flow when reverse biased.
Forward biased: voltage drop across diode, current flows
Reverse biased: no current flow, diode acts as open circuit
I applied via LinkedIn and was interviewed in Jul 2024. There were 4 interview rounds.
Previous work clarity is essential for successful collaboration and understanding of project requirements.
Clearly explain the projects you have worked on in the past, including your role and responsibilities
Provide examples of how you communicated with team members to ensure clarity in project goals
Discuss any challenges you faced in previous projects and how you overcame them
Bit manipulation, memory layout, interrupts, semaphore mutex, implement memcpy, sorting, algo to share resource equally
I applied via Naukri.com and was interviewed in Mar 2024. There were 4 interview rounds.
I applied via Naukri.com and was interviewed in Aug 2024. There was 1 interview round.
Basic java programs based on strings and arrays
based on 1 review
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L2 Engineer
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Asic Design Engineer
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Senior Physical Design Engineer
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| ₹30 L/yr - ₹45 L/yr |
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