Premium Employer

i

This company page is being actively managed by Alphawave Semi Team. If you also belong to the team, you can get access from here

Alphawave Semi

Compare button icon Compare button icon Compare
1.0

based on 1 Review

i

This rating is based on a small number of reviews, so it may not fully reflect the overall employee experience.

Filter interviews by

Alphawave Semi Interview Questions and Answers

Updated 22 Nov 2024

Alphawave Semi Interview Experiences

1 interview found

Interview experience
5
Excellent
Difficulty level
Moderate
Process Duration
Less than 2 weeks
Result
Not Selected

I applied via Recruitment Consulltant and was interviewed in May 2024. There were 3 interview rounds.

Round 1 - Aptitude Test 

Online Test which consists of Aptitude, Reasoning, Electronic Circuits and PD questions

Round 2 - One-on-one 

(2 Questions)

  • Q1. Explain the PD flow and checks at each at every stage ?
  • Ans. 

    Physical Design flow involves multiple stages with various checks to ensure design quality and manufacturability.

    • Synthesis: Logic synthesis to convert RTL to gate-level netlist.

    • Floorplanning: Define chip area, placement of blocks, and power grid.

    • Placement: Place standard cells in the floorplan area.

    • Clock Tree Synthesis: Build clock distribution network for timing.

    • Routing: Connect the placed cells with metal layers.

    • Desi...

  • Answered by AI
  • Q2. Questions related to timing like setup,hold ??
Round 3 - HR 

(2 Questions)

  • Q1. Tell me about ur self??
  • Ans. 

    I am a dedicated and experienced Physical Design Engineer with a strong background in designing and optimizing integrated circuits.

    • I have a Bachelor's degree in Electrical Engineering from XYZ University.

    • I have worked at ABC Semiconductor for 5 years, where I led the physical design team for multiple successful projects.

    • I am proficient in tools like Cadence Virtuoso and Synopsys ICC.

    • I have a strong understanding of tim...

  • Answered by AI
  • Q2. Explain the operation of NAND gate using CMOS , transformer circuits etc...?
  • Ans. 

    NAND gate can be implemented using CMOS technology, which involves using both NMOS and PMOS transistors in parallel.

    • NAND gate consists of multiple transistors connected in series and parallel to achieve the desired logic function.

    • In CMOS implementation, NMOS transistors are used for the pull-down network while PMOS transistors are used for the pull-up network.

    • When any of the inputs is low, the corresponding NMOS transi...

  • Answered by AI

Interview Preparation Tips

Interview preparation tips for other job seekers - Focus on basics and prepare electronic circuits well.... These are foundation for any job interview

Physical Design Engineer Interview Questions asked at other Companies

Q1. What are the conditions for an RC circuit to work as an integrator/differentiator Can you derive it with this circuit
View answer (1)

Interview questions from similar companies

Interview experience
3
Average
Difficulty level
Moderate
Process Duration
2-4 weeks
Result
No response

I applied via Referral and was interviewed in Sep 2024. There were 2 interview rounds.

Round 1 - Technical 

(5 Questions)

  • Q1. For the first round t is only only.
  • Q2. UVM-Phases,config db,resource db,asked me to write code for my projects mentioned in resume
  • Q3. AMBA protocols(mentioned in resume) pslave error,decode error,signals,arbitration,interleaving.
  • Q4. UVM architecture,verification flow
  • Q5. First round mostly focussed on my communication skills and projects mentioned in my resume.For my friend they showed a PPT of questions just followed them.
Round 2 - Technical 

(4 Questions)

  • Q1. It is a face to face interview,Only focussed on technical questions.They have a common ppt with technical questions .They will show those questions ask you to write answers on a paper.
  • Q2. 1.waveform shown asked to find the expression-XOR gate. 2.parity checker and parity generator truthtable and verilog code. 3.modports,clocking blocks and interface sv code. for (addr=something,data=somethi...
  • Q3. Verilog FIFO code Assertion waveform shown sv code for it APB protocol waveforms Protocols signals if you mention them protocol address calculations coverage code types of array and their syntax
  • Q4. For technical round they focus on coding only,don't forget to see all sv topics coding structure.
Interview experience
1
Bad
Difficulty level
Moderate
Process Duration
Less than 2 weeks
Result
No response

I applied via Walk-in and was interviewed in Oct 2024. There were 3 interview rounds.

Round 1 - Technical 

(5 Questions)

  • Q1. OOPS concept and All Major pillars with Scanrio-based questions asked on Abstract class and Interface
  • Q2. .Net MVC and .Net Core based on program.cs file and Dependency Injection and Middleware in deep
  • Q3. Pattern question and check string Palindrome
  • Q4. SQL Queries around 4th highest salary of Employee
  • Q5. All basic programming concept checking like having prefix and postfix expression problem solving on paper
Round 2 - Technical 

(4 Questions)

  • Q1. TechnoManagerial Round Collection question to find about number of character present in the word Mirafra with live coding F2F
  • Q2. API testing ang REST API Concept
  • Q3. Professional Journey
  • Q4. Project Details
Round 3 - Technical 

(2 Questions)

  • Q1. It was a director round but say you need to give again technical round ,they wasted my time and money.
  • Q2. SQL Queries on pen and paper

Interview Preparation Tips

Interview preparation tips for other job seekers - HR said you haven't the skill to represent on client. Never believe on HR what they said.Final round was my Director's round but she wasted my time
Interview experience
5
Excellent
Difficulty level
Moderate
Process Duration
Less than 2 weeks
Result
Selected Selected

I applied via Recruitment Consulltant and was interviewed in Oct 2024. There were 3 interview rounds.

Round 1 - Aptitude Test 

We have 25 questions and negative marking is there

Round 2 - Technical 

(2 Questions)

  • Q1. What are storage classes in c language?
  • Ans. 

    Storage classes in C language define the scope and lifetime of variables.

    • There are four storage classes in C: auto, register, static, and extern.

    • Auto variables are local to the block they are declared in and have automatic storage duration.

    • Register variables are stored in CPU registers for faster access.

    • Static variables retain their value between function calls.

    • Extern variables are declared outside of any function and ...

  • Answered by AI
  • Q2. How many address lines are present in 1kb memory?
  • Ans. 

    There are 10 address lines present in 1kb memory.

    • 1kb memory = 1024 bytes

    • To address 1024 bytes, 10 address lines are needed (2^10 = 1024)

  • Answered by AI
Round 3 - Technical 

(2 Questions)

  • Q1. Program on array , reverse the array
  • Ans. 

    Reverse an array of strings

    • Create a new array to store the reversed strings

    • Iterate through the original array in reverse order and add each element to the new array

    • Return the new array as the reversed array

  • Answered by AI
  • Q2. Logic gates, what is the output of this .they will ask by showing picture

Skills evaluated in this interview

Interview experience
3
Average
Difficulty level
-
Process Duration
Less than 2 weeks
Result
Not Selected

I was interviewed in Oct 2024.

Round 1 - Technical 

(5 Questions)

  • Q1. Describe the PD flow
  • Ans. 

    The PD flow is the process of designing the physical layout of integrated circuits.

    • Initial floorplanning to determine the placement of blocks and macros

    • Placement and optimization of standard cells

    • Routing of interconnects to connect the various components

    • Physical verification to ensure design rules are met

    • Timing closure to meet performance targets

  • Answered by AI
  • Q2. How to fix setup and hold violation
  • Ans. 

    Setup and hold violations can be fixed by adjusting timing constraints, optimizing clock tree, and redesigning critical paths.

    • Adjust timing constraints to allow more time for signals to propagate

    • Optimize clock tree to reduce clock skew and improve timing

    • Redesign critical paths by adding buffers or restructuring logic

    • Use ECO (Engineering Change Order) to make necessary changes without redoing the entire design

  • Answered by AI
  • Q3. What is you domain experties
  • Ans. 

    My domain expertise is in physical design engineering, specifically in the areas of floorplanning, placement, routing, and timing closure.

    • Floorplanning

    • Placement

    • Routing

    • Timing closure

  • Answered by AI
  • Q4. Why are you looking for job switch
  • Q5. Why does setup and hold ail on same path
  • Ans. 

    Setup and hold time violations can occur on the same path due to different reasons.

    • Timing violations can occur due to variations in process, voltage, and temperature (PVT)

    • Clock skew between different paths can lead to setup and hold violations on the same path

    • Issues with clock tree synthesis or routing can also contribute to setup and hold time violations

    • Improper constraints or incorrect timing analysis setup can resul

  • Answered by AI
Interview experience
2
Poor
Difficulty level
-
Process Duration
-
Result
-
Round 1 - Coding Test 

I am asked to give the coding test and tech questions on resume and job description

Round 2 - Technical 

(2 Questions)

  • Q1. Domain test questions are asked
  • Q2. Behaviour questions are asked
Interview experience
5
Excellent
Difficulty level
Moderate
Process Duration
Less than 2 weeks
Result
Not Selected

I applied via campus placement at RV College Of Engineering (RVCE) and was interviewed in Sep 2024. There were 3 interview rounds.

Round 1 - Aptitude Test 

General aptitude questions. Easy to solve. Didn’t take much time

Round 2 - Technical 

(2 Questions)

  • Q1. Explain operation of rc circuit
  • Ans. 

    An RC circuit consists of a resistor and a capacitor connected in series or parallel, used for filtering, timing, and signal processing.

    • RC circuit operation is based on the charging and discharging of the capacitor through the resistor.

    • When a voltage is applied to the circuit, the capacitor charges up to the applied voltage through the resistor.

    • The time constant (RC) determines how quickly the capacitor charges or disc...

  • Answered by AI
  • Q2. Draw waveform for diode
  • Ans. 

    A diode waveform typically shows a voltage drop when forward biased and no current flow when reverse biased.

    • Forward biased: voltage drop across diode, current flows

    • Reverse biased: no current flow, diode acts as open circuit

  • Answered by AI
Round 3 - Technical 

(1 Question)

  • Q1. Questions based on my project

Interview Preparation Tips

Interview preparation tips for other job seekers - Brush up your basics of analog and digital electronics
Interview experience
4
Good
Difficulty level
Moderate
Process Duration
Less than 2 weeks
Result
Selected Selected

I applied via LinkedIn and was interviewed in Jul 2024. There were 4 interview rounds.

Round 1 - Technical 

(2 Questions)

  • Q1. Ofdm, Fixed point, sampling theorem, digital filters,
  • Q2. Previous work clarity
  • Ans. 

    Previous work clarity is essential for successful collaboration and understanding of project requirements.

    • Clearly explain the projects you have worked on in the past, including your role and responsibilities

    • Provide examples of how you communicated with team members to ensure clarity in project goals

    • Discuss any challenges you faced in previous projects and how you overcame them

  • Answered by AI
Round 2 - Technical 

(2 Questions)

  • Q1. Fft, ofdm, CP, sampling theorem, previous experience,
  • Q2. C basics, memory layout, function pointer, big small endian, bit manipulation, zero padding in structures
Round 3 - Coding Test 

Bit manipulation, memory layout, interrupts, semaphore mutex, implement memcpy, sorting, algo to share resource equally

Round 4 - One-on-one 

(1 Question)

  • Q1. Previous work experience, general attitude

Interview Preparation Tips

Interview preparation tips for other job seekers - Prepare well for coding, strong on basics
Interview experience
5
Excellent
Difficulty level
Moderate
Process Duration
6-8 weeks
Result
Selected Selected

I applied via Naukri.com and was interviewed in Mar 2024. There were 4 interview rounds.

Round 1 - Resume Shortlist 
Pro Tip by AmbitionBox:
Keep your resume crisp and to the point. A recruiter looks at your resume for an average of 6 seconds, make sure to leave the best impression.
View all tips
Round 2 - HR 

(1 Question)

  • Q1. Your previous experience details.
Round 3 - Technical 

(2 Questions)

  • Q1. Al questions regarding electrical and electronics components and Measurement instruments specifications
  • Q2. Electrical and electronics components and all industrial automationparts and test and measurementinstruments experience.
Round 4 - One-on-one 

(2 Questions)

  • Q1. About Salary details and company rules.
  • Q2. 7.5 lakh and US shift 5:30pm to 2:30am
Interview experience
4
Good
Difficulty level
Easy
Process Duration
2-4 weeks
Result
Selected Selected

I applied via Naukri.com and was interviewed in Aug 2024. There was 1 interview round.

Round 1 - Coding Test 

Basic java programs based on strings and arrays

Alphawave Semi Interview FAQs

How many rounds are there in Alphawave Semi interview?
Alphawave Semi interview process usually has 3 rounds. The most common rounds in the Alphawave Semi interview process are Aptitude Test, One-on-one Round and HR.
What are the top questions asked in Alphawave Semi interview?

Some of the top questions asked at the Alphawave Semi interview -

  1. Explain the PD flow and checks at each at every stag...read more
  2. Explain the operation of NAND gate using CMOS , transformer circuits etc....read more
  3. Questions related to timing like setup,hold...read more

Tell us how to improve this page.

Join Alphawave Semi Leading the world in high-speed connectivity solutions

Interview Questions from Similar Companies

Intel Interview Questions
4.2
 • 217 Interviews
Nvidia Interview Questions
3.7
 • 102 Interviews
Broadcom Interview Questions
3.3
 • 41 Interviews
Analog Devices Interview Questions
4.1
 • 24 Interviews
View all

Alphawave Semi Reviews and Ratings

based on 1 review

1.0/5

Rating in categories

2.0

Skill development

1.0

Work-Life balance

3.0

Salary & Benefits

2.0

Job Security

1.0

Company culture

2.0

Promotions/Appraisal

1.0

Work Satisfaction

Explore 1 Review and Rating
L2 Engineer
4 salaries
unlock blur

₹19 L/yr - ₹30 L/yr

Asic Design Engineer
3 salaries
unlock blur

₹1 L/yr - ₹17 L/yr

Senior Physical Design Engineer
3 salaries
unlock blur

₹30 L/yr - ₹45 L/yr

Explore more salaries
Compare Alphawave Semi with

Intel

4.3
Compare

Broadcom

3.3
Compare

Nvidia

3.7
Compare

Advanced Micro Devices

3.8
Compare

Calculate your in-hand salary

Confused about how your in-hand salary is calculated? Enter your annual salary (CTC) and get your in-hand salary
Did you find this page helpful?
Yes No
write
Share an Interview