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LeadSoc Technologies India
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LeadSoc Technologies India Physical Design Engineer Interview Questions, Process, and Tips
LeadSoc Technologies India Physical Design Engineer Interview Experiences
1 interview found
I appeared for an interview in Oct 2024.
(5 Questions)
- Q1. Describe the PD flow
- Ans.
The PD flow is the process of designing the physical layout of integrated circuits.
Initial floorplanning to determine the placement of blocks and macros
Placement and optimization of standard cells
Routing of interconnects to connect the various components
Physical verification to ensure design rules are met
Timing closure to meet performance targets
- Q2. How to fix setup and hold violation
- Ans.
Setup and hold violations can be fixed by adjusting timing constraints, optimizing clock tree, and redesigning critical paths.
Adjust timing constraints to allow more time for signals to propagate
Optimize clock tree to reduce clock skew and improve timing
Redesign critical paths by adding buffers or restructuring logic
Use ECO (Engineering Change Order) to make necessary changes without redoing the entire design
- Q3. What is you domain experties
- Ans.
My domain expertise is in physical design engineering, specifically in the areas of floorplanning, placement, routing, and timing closure.
Floorplanning
Placement
Routing
Timing closure
- Q4. Why are you looking for job switch
- Q5. Why does setup and hold ail on same path
- Ans.
Setup and hold time violations can occur on the same path due to different reasons.
Timing violations can occur due to variations in process, voltage, and temperature (PVT)
Clock skew between different paths can lead to setup and hold violations on the same path
Issues with clock tree synthesis or routing can also contribute to setup and hold time violations
Improper constraints or incorrect timing analysis setup can resul
Physical Design Engineer Jobs at LeadSoc Technologies India
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Physical Design Engineer Interview Questions & Answers
Mirafra Technologies
Anonymous
posted on 1 Nov 2022
I applied via Referral and was interviewed before Nov 2021. There were 2 interview rounds.
(2 Questions)
- Q1. Interview based on EMIR ànalysis 1. Static and Dynamic Ir drop questions
- Q2. Power and signal EM questions
Interview Preparation Tips
(1 Question)
- Q1. Sdc basics TCL coding
I applied via Campus Placement and was interviewed in Aug 2024. There were 3 interview rounds.
Aotitude,core que on all subjects in ece
(2 Questions)
- Q1. INTERNSHIP EXPERIENCE
- Ans.
I completed a 6-month internship at XYZ Company where I gained hands-on experience in physical design tools and methodologies.
Worked on floorplanning, placement, and routing of digital designs
Utilized tools such as Cadence Innovus and Synopsys ICC
Collaborated with cross-functional teams to optimize design performance
- Q2. ON DSD,VLSI,ANALOG ELECTRONICS
(2 Questions)
- Q1. APTITUDE,MATH,VLSI,DSD
- Q2. VLSI (HARD QUESTION BASED ON INDUSTRY LEVEL LIKE ON CIRCUIT HE GIVES ONE SCENARIO U HAVE TO ANSWER IT)
Interview Preparation Tips
(1 Question)
- Q1. Congestion analysis
I applied via Campus Placement and was interviewed before Jan 2021. There were 3 interview rounds.
(1 Question)
- Q1. What is a cache? What does tag used for in a cache?
- Ans.
A cache is a high-speed data storage layer that stores frequently accessed data to reduce access time. A tag is used to identify the location of data in the cache.
Cache is a temporary storage that holds frequently accessed data
It reduces the access time by providing faster access to data
Tag is used to identify the location of data in the cache
Tag is a part of the cache memory address
Cache can be implemented in hardware...
C Coding questions
(3 Questions)
- Q1. What is your family background?
- Q2. What are your strengths and weaknesses?
- Q3. Tell me about yourself.
Interview Preparation Tips
Skills evaluated in this interview
I applied via Referral and was interviewed before Jun 2021. There were 2 interview rounds.
They asked are u able to work for 12-13 hours and give 3 to 4 simple maths questions in written to solve . They asked for having any health issues because if u r not physically fit then not able to work for 12 to 13 hours a day. A perfect professional company just for earning profit nothing is good for the engineer or workers .
A one line for Apar industry - "Naam bade aur darshan chhote ". Only the hard one survive there if 20 persons start the job , after a year only 2 or 3 person able to survive there .
(2 Questions)
- Q1. Simple question about your home background.
- Q2. Yours qualifications and ur father qualifications etc .
Interview Preparation Tips
Interview Preparation Tips
Experience: Questions were from digital Electronics which included realization of counters using JK FF,Sequence detector,Boolean expression reduction,One shot and drawing waveforms of some digital circuits.Questions were also their from pipelinig,finding out MIPS,power consumption of two processors,Small signal analysis of MOSFETs,Buffer using CMOS ,finding out the type of filter given block diagram(control theory).Questions were easy and required step by step realization.
Tips: Prepare digital Electronics very well as it has 50% weightage in paper. Pipelinig is important. Some basics concepts of CMOS is very necessary.
Duration: 1hr 15 min minute
Total Questions: 12
Round: Technical Interview
Experience: First they asked to introduce yourself.
Then they asked about projects & Internship.
STA,EEPROM,EPROM,DRAM,SRAM,CACHE Memory,Pipelining,DMA was asked in depth.
Difference between clock skew and Jitter.
Asked whether I know any Hardware Languages.
XOR gate using 2:1 MUX.
Gave a waveform,had to realize using DFF and considering the delay.
Tips: Study STA very well.
Questions will be asked in depth from any topic.
Round: HR Interview
Experience: Family Background
Why NXP
Hobbies
Skill Tips: Study Digital Electronics very well
Skills: Analog Electronics, Microprocessor, Vlsi Basics, Digital Circuits
College Name: BIT Mesra
Saba
Interview Preparation Tips
Experience: Questions were from Digital Electronics,Microprocessors and some from CMOS.
50% Digital Electronics.
1 X Output waveform drawing from circuit of FFs & gates
1 X Realize inverter from given two blocks
1 X CMOS implementation of gates
1 X Realize digital circuit for given waveform
1 X MIPS & Pipelining
1 X Processors power Dissipation calculation
1 X Small Signal analysis of CMOS
1 X Compare two given buffers circuits(CMOS)
1 X Transfer function calculation(Control Theory)
1 X Counter using JK FF
1 X Sequence Detector
Tips: Study digital electronics very well.
Duration: 1 hr 45 min minute
Total Questions: 12
Round: Technical Interview
Experience: Indroduction
Projects & Internship
Discussions in DEPTH on:
Pipelining
STA
MIPS
Memory(flash memory,DRAM,SRAM)
CACHE Memory
DMA
Digital circuit realization for given waveform
XOR Gate using 2:1 MUX
Tips: Prepare Digital electronics and Microprocessors very well.Sta is very important.Panel will go deep into the topics to check ur technical knowledge.
TIPS: Be confident and your opinion should be strong.Stand by what you say.Do not get confused.And when panel asks to solve any digital circuits, speak loud what is in your mind and what approach you are using.Be honest.
Round: HR Interview
Experience: Family Background
Why Freescale
Skills: Static Timing Analysis (STA), Memory, CMOS Circuits, Microprocessor, Digital Circuits
College Name: BIT Mesra
Motivation: I had interest in core electronics
Design Engineer Interview Questions & Answers
Texas Instruments
Sai Vihari Chaturvedula
posted on 28 Aug 2016
I applied via Campus Placement
Interview Preparation Tips
Experience: Resume is not given any due importance in selection for further rounds . But honesty is very important as it counts once you are selected for HR round .
Tips: Try to be one hundred percent honest . And put your projects and course work in the beginning. They don't care your POR s and extra curricular activities.
Round: Test
Experience: Hardware - Questions are mainly from ELECTRICAL CIRCUITS (RLC ckts) , Analog ckts. Amplifiers , Opamps , digital system design . Aptitude section is very easy . Hardware section is tough .I felt Signal processing was easier , indeed I got selected for that profile .
Tips: Prepare thoroughly these courses :- EMC , DIGITAL SYSTEMS, NETWORKS AND SYSTEMS,ANALOG & DIGITAL SIGNAL PROCESSING , ANALOG CKTS COURSES .THAT SHOULD BE ENOUGH .
Duration: 90 - Signal Processing minutes
Total Questions: 120 - Hardware and aptitude
Round: Group Discussion
Experience: No
Tips: No
Duration: 2
College Name: IIT Madras
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LeadSoc Technologies India Physical Design Engineer Interview Process
based on 1 interview
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LeadSoc Technologies India Physical Design Engineer Reviews and Ratings
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Rating in categories
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Physical Design Engineer
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|  ₹6.5 L/yr - ₹26.8 L/yr |
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