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Flip flops and latches are both sequential logic circuits, but flip flops are edge-triggered while latches are level-triggered.
Flip flops are edge-triggered, meaning they change state only on a clock edge.
Latches are level-triggered, meaning they change state as long as the enable signal is active.
Flip flops are more commonly used in synchronous systems for data storage and transfer.
Latches are simpler in design and fa...
Verilog is a hardware description language used for digital circuit design, while SystemVerilog is an extension that adds features for verification and design.
Verilog is used for digital circuit design, while SystemVerilog is used for verification and design
SystemVerilog includes features like classes, randomization, and assertions for verification purposes
Verilog is more focused on describing the behavior of hardware ...
I applied via Naukri.com and was interviewed in Aug 2024. There were 5 interview rounds.
Kindly plan to -Online mode
I have experience working in a fast-paced environment with high workload, handling multiple projects simultaneously.
Managed workload effectively by prioritizing tasks based on deadlines and importance
Collaborated with team members to ensure projects were completed on time and within budget
Background in designing mechanical components for automotive industry at XYZ Company
Experience working on projects with tight deadli
Pratical rest in design related
Group discussion with management team
I applied via LinkedIn and was interviewed in Mar 2024. There were 2 interview rounds.
Verilog code for a mod 3 counter is a sequential circuit that counts in binary from 0 to 2 and then resets to 0.
Use a 2-bit register to store the current count value.
Increment the count value on each clock cycle.
Reset the count value to 0 when it reaches 3.
Set and hold slack are calculated by subtracting the required time from the actual time for setup and hold constraints.
Set slack = Actual arrival time - Required arrival time for setup constraint
Hold slack = Required arrival time - Actual arrival time for hold constraint
Positive slack indicates the timing constraint is met, negative slack indicates violation
Example: Set slack = 0.2ns, Hold slack = -0.1ns
As a Design Engineer in my current company, my roles and responsibilities include designing and developing new products, collaborating with cross-functional teams, conducting research and analysis, and ensuring compliance with industry standards.
Designing and developing new products
Collaborating with cross-functional teams
Conducting research and analysis
Ensuring compliance with industry standards
E2E ECC (End-to-End Error Correction Code) is implemented through algorithms that detect and correct errors in data transmission.
E2E ECC algorithms are used to ensure data integrity from the source to the destination.
These algorithms add redundant bits to the data being transmitted, allowing for error detection and correction.
Examples of E2E ECC algorithms include Reed-Solomon codes and Hamming codes.
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Wipro interview questions for designations
Asynchronous FIFO counter code is used to implement a FIFO buffer with asynchronous read and write operations.
Asynchronous FIFO is a type of FIFO buffer where the read and write operations are not synchronized.
The counter code is used to keep track of the number of elements in the FIFO buffer.
Example code snippet: int counter = 0; // Initialize counter for FIFO buffer
Get interview-ready with Top Wipro Interview Questions
I applied via Naukri.com and was interviewed in Mar 2022. There were 2 interview rounds.
Logical thinking
Honesty is still the best policy in today's world.
Honesty builds trust and credibility in personal and professional relationships.
Being honest promotes transparency and accountability.
Honesty fosters a positive work culture and encourages ethical behavior.
Examples: Companies that prioritize honesty in their operations tend to have better customer satisfaction and employee retention rates.
Examples: Honesty in financial ...
To enable data factory, you need to create a data factory resource in Azure and configure it with linked services, datasets, and pipelines.
Create a data factory resource in Azure portal
Configure linked services to connect to data sources and destinations
Define datasets to represent the data you want to process
Create pipelines to orchestrate the movement and transformation of data
Monitor and manage the data factory usin
To disable data factory, you can stop or delete the data factory resources.
Stop or delete the data factory pipelines and triggers
Deallocate or delete the data factory linked services
Disable or delete the data factory datasets and data flows
I applied via Naukri.com and was interviewed before Oct 2020. There was 1 interview round.
I applied via LinkedIn and was interviewed in Mar 2022. There were 2 interview rounds.
It will be a bit hard. But it contains some basic algorithm questions pseudo solving nd problem solving
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2 Interview rounds
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